PIC12C672 MICROCHIP [Microchip Technology], PIC12C672 Datasheet - Page 77

• Manufacturer Part Number: PIC12C672
• Description: 8-Pin, 8-Bit CMOS Microcontroller with EEPROM Data Memory
• Manufacturer: MICROCHIP [Microchip Technology]

14.0
The following routines are written for 4 MHz clock oper-
ation, where the worst case timing occurs; the routines
can be used at lower frequencies without modification.
For those using clock speeds much less than 4MHz, it
may be possible to reduce code size by removing some
of the NOPs (see code listing).
14.1
The EEPROM interface is a 2-wire bus protocol con-
sisting of data (SDA) and a clock (SCL). Although
these lines are mapped into the GPIO register, they are
not accessible as external pins; only to the internal
EEPROM peripheral. SDA and SCL operation is also
slightly different than GPO-GP5 as listed below.
Namely, to avoid code overhead in modifying the TRIS
register, both SDA and SCL are always outputs. To
read data from the EEPROM peripheral requires out-
putting a ‘1’ on SDA placing it in high-Z state, where
only the internal 100K pull-up is active on the SDA line.
14.2
#include <p12CE518.inc>
;
;
;
;
;
; PIC12CE51X EEPROM communication code.
; with the application.
; write byte random address
; read byte random address
; read byte next address
;
; read sequential is not supported.
;
; If the operation is successful, bit 7 of PC_OFFSET will be set, and
; the functions will return W=1.
; cycle, it will not ACK the command.
; bit 7 of PC_OFFSET cleared and and W will be set to 0.
;
; Based on Franco code.
;
; Must reside on the lower half of code page (address 0-FF).
;
; This provides users with highly compressed assembly code for
; communication between the EEPROM and the Microcontroller, which
; leaves a maximum amount of code space for the core application.
1997 Microchip Technology Inc.
SDA:
SCL:
TITLE "PIC with EEPROM Data Memory Interface"
LIST P=12CE518
APPENDIX A
SDA and SCL
Example Code for Reading/Writing to EEPROM Data Memory
Program:
Revision Date:
Built-in 100K pull-up to VDD
Open-drain (pull-down only)
Always an output, regardless of TRIS<6>
Outputs a ‘1’ on reset
Full CMOS output
Always an output regardless of TRIS<7>
Outputs a ‘1’ on reset
These routines provide the following functionality:
EEPROM.ASM
10-10-97
If the memory is busy with a write
; Change to 12CE519 if using PIC12CE519
The functions will return with
Adapted to 12CE51x parts
This code should be linked in
Preliminary
The following example requires:
• Code Space: 77 words
• RAM Space: 5 bytes (4 are overlayable)
• Stack Levels:1 (The call to the function itself. The
• Timing:
• IO Pins: 0 (No external IO pins are used)
This code must reside in the lower half of a page. The
code achieves it’s small size without additional calls
through the use of a sequencing table. The table is a
list of procedures that must be called in order. The
table uses an ADDWF PCL,F instruction, effectively a
computed goto, to sequence to the next procedure.
However the ADDWF PCL,F instruction yields an 8 bit
address, forcing the code to reside in the first 256
addresses of a page.
functions do not call any lower level functions.)
- WRITE_BYTE takes 328 cycles
- READ_CURRENT takes 212 cycles
- READ_RANDOM takes 416 cycles.
PIC12CE5XX
DS40172A-page 77