MPC8308CVMADDA FREESCALE [Freescale Semiconductor, Inc], MPC8308CVMADDA Datasheet - Page 25
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MPC8308CVMADDA
Manufacturer Part Number
MPC8308CVMADDA
Description
MPC8308 PowerQUICC II Pro Processor Hardware Specification
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MPC8308CVMADDA.pdf
(88 pages)
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To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV p-p, which is referred as the single-ended swing for each signal. In this example, since
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V
between 500 mV and –500 mV, in other words, V
phase. The peak differential voltage (V
is 1000 mV p-p.
10.2
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks input is SD_REF_CLK and SD_REF_CLK
for PCI Express.
The following sections describe the SerDes reference clock requirements and some application
information.
10.2.1
Figure 16
Freescale Semiconductor
OD
7. Common Mode Voltage, V
) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
A Volts
B Volts
The Common Mode Voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output, V
+ V
within a differential pair. In a system, the common mode voltage may often differ from one
component’s output to the other’s input. Sometimes, it may be even different between the receiver
input and driver output circuits within the same component. It is also referred as the DC offset in
some occasion.
SerDes Reference Clocks
shows a receiver reference diagram of the SerDes reference clocks.
TXn
SerDes Reference Clock Receiver Characteristics
)/2 = (A + B) / 2, which is the arithmetic mean of the two complimentary output voltages
Figure 15. Differential Voltage Definitions for Transmitter or Receiver
MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 0
TXn or RXn
TXn or RXn
Differential Peak-Peak Voltage, V
cm
DIFFp
Differential Swing, V
Differential Peak Voltage, V
) is 500 mV. The peak-to-peak differential voltage (V
OD
is 500 mV in one phase and –500 mV in the other
ID
or V
DIFFpp
OD
DIFFp
= 2*V
= A – B
= |A – B|
DIFFp
(not shown)
High-Speed Serial Interfaces (HSSI)
V
cm
= (A + B) / 2
cm_out
= (V
DIFFp-p
TXn
25
)