A80960HA25SL2GX INTEL [Intel Corporation], A80960HA25SL2GX Datasheet - Page 71
A80960HA25SL2GX
Manufacturer Part Number
A80960HA25SL2GX
Description
80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.A80960HA25SL2GX.pdf
(102 pages)
- Current page: 71 of 102
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Advance Information
Figure 48. Terminating a Burst with BTERM
BE3:0, LOCK
A31:4, SUP,
CT3:0, D/C,
Datasheet
READY
BTERM
BLAST
PCHK
CLKIN
D31:0,
DP3:0
WAIT
DT/R
ADS
DEN
A3:2
W/R
Note: READY adds memory access time to data transfers, whether or not the
bus access is a burst access. BTERM interrupts a bus access, whether or not
the bus access has more data transfers pending. Either the READY signal or
the BTERM signal terminates a bus access when the signal is asserted during
the last (or only) data transfer of the bus access.
A
D
00
1
D0
A
N
RAD
Quad-Word Read Request
D
01
= 0, N
Ready Enabled
1
Valid
D1
RDD
A
= 0, N
See Note
D
10
RDA
= 0
1
D2
D
11
1
D3
80960HA/HD/HT
65
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