A80960HA25SL2GX INTEL [Intel Corporation], A80960HA25SL2GX Datasheet - Page 81

• Manufacturer Part Number: A80960HA25SL2GX
• Description: 80960HA/HD/HT 32-Bit High-Performance Superscalar Processor
• Manufacturer: INTEL [Intel Corporation]

Advance Information
Figure 59. Bus States
!RESET and
!HOLD and
REQUEST
ONCE and
RESET
1. When the PMCON for the region has External Ready Control enabled, wait states are inserted as
2. W
3. W
4. W
BOFF
RESET
To
long as READY and BTERM are de-asserted. When Read Pipelining is enabled, the Ta state of the
subsequent read access is concurrent with the last data cycle of the access. Because External
Ready Control is disabled for Read Pipelining, the address cycle occurs during BLAST.
a
d
x
CNT is decremented during T
CNT is decremented during T
CNT is decremented during T
Datasheet
RESET and
Tb
!ONCE
!BOFF
Ti
BOFF
Ta
READ and N
WRITE and N
Taw
2
!HOLD and W
and !REQUEST
W
a
!BOFF and READY and !BLAST or
!BOFF and BTERM and !BLAST or !BOFF and
!HOLD and BLAST and REQUEST and N
!HOLD and W
and REQUEST
CNT > 1
rad
wad
!BOFF and READ and N
!BOFF and WRITE and N
> 0 or
> 0
!HOLD
x
HOLD
CNT=1
aw
rw
dw
x
CNT=1
W
HOLD
a
CNT = 1
BOFF
Th
NOTE:
W
rad
wad
x
CNT=1 and
= 0 or
HOLD
= 0
N
!BOFF and
BLAST and
xda
XDA
> 0
= 0
Trw
4
!BOFF and
HOLD and BLAST
and N
Td
1
W
xda
d
CNT = 1
W
= 0
x
CNT > 1
!BOFF and READ and N
and !BLAST or !BOFF and
WRITE and N
READ and N
WRITE and N
READY!
KEY:
To = ONCE
Ti = IDLE
Th = HOLD
Ta = ADDRESS
Td = DATA
Tb = BOFF’ed
Taw= address to data wait
Tdw= data to data wait
Tdw= data to address wait
REQUEST= One or more
requests in the bus queue.
READ= The current
access is a read.
WRITE= The current
access is a write.
80960HA/HD/HT
Tdw
!BOFF and !HOLD and
BLAST and
and !REQUEST
wdd
rdd
3
wdd
= 0 and !BLAST or
> 0 or
> 0
W
rdd
N
xda
d
CNT > 1
= 0
= 0
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