CY8C38_11 CYPRESS [Cypress Semiconductor], CY8C38_11 Datasheet - Page 13

• Manufacturer Part Number: CY8C38_11
• Manufacturer: CYPRESS [Cypress Semiconductor]

Table 4-2. Logical Instructions (continued)
4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
Table 4-3. Data Transfer Instructions
Document Number: 001-11729 Rev. *R
ANL
ORL
ORL
ORL
ORL
ORL
ORL
XRL
XRL
XRL
XRL
XRL
XRL
CLR
CPL
RL
RLC
RR
RRC A
SWAP A
MOV A,Rn
MOV A,Direct
MOV A,@Ri
MOV A,#data
MOV
MOV
MOV
MOV
MOV
Direct, #data
A,Rn
A,Direct
A,@Ri
A,#data
Direct, A
Direct, #data
A
A,Rn
A,Direct
A,@Ri
A,#data
Direct, A
Direct, #data
A
A
A
A
Rn,A
Rn,Direct
Rn, #data
Direct, A
Direct, Rn
Mnemonic
Mnemonic
AND immediate data to direct byte
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
OR immediate data to direct byte
XOR register to accumulator
XOR direct byte to accumulator
XOR indirect RAM to accumulator
XOR immediate data to accumulator
XOR accumulator to direct byte
XOR immediate data to direct byte
Clear accumulator
Complement accumulator
Rotate accumulator left
Rotate accumulator left through carry
Rotate accumulator right
Rotate accumulator right though carry
Swap nibbles within accumulator
Move register to accumulator
Move direct byte to accumulator
Move indirect RAM to accumulator
Move immediate data to accumulator
Move accumulator to register
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Description
Description
addressing mode.
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions.
the available Boolean instructions.
Table 4-3
PSoC
lists the various data transfer
®
3: CY8C38 Family
Bytes
Bytes
3
1
2
1
2
2
3
1
2
1
2
2
3
1
1
1
1
1
1
1
1
2
1
2
1
2
2
2
2
Data Sheet
Page 13 of 129
Table 4-4
Cycles
Cycles
3
1
2
2
2
3
3
1
2
2
2
3
3
1
1
1
1
1
1
1
1
2
2
2
1
3
2
2
2
lists
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