CY8C38_11 CYPRESS [Cypress Semiconductor], CY8C38_11 Datasheet - Page 18

• Manufacturer Part Number: CY8C38_11
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document Number: 001-11729 Rev. *R
Notes
The total interrupt latency (ISR execution)
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
ACTIVE_INT_NUM
INT_VECT_ADDR
= 12 cycles
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
INT_INPUT
PEND
POST
(#10)
CLK
IRA
IRQ
IRC
1
Interrupt generation and posting to CPU
Arrival of new Interrupt
2
Pend bit is set on next system clock active edge
NA
NA
3
Interrupt is posted to ascertain the priority
4
Interrupt request sent to core for processing
5
CPU Response
address is posted to core
The active interrupt ISR
Figure 4-2. Interrupt Processing Timing Diagram
0x0010
6
Int. State
number is posted to core
Clear
The active interrupt
7
IRQ cleared after receiving IRA
8
Completing current instruction and branching to vector address
9
POST and PEND bits cleared after IRQ is sleared
NA
10
PSoC
Complete ISR and return
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Data Sheet
Page 18 of 129
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