DP83848YB_08 NSC [National Semiconductor], DP83848YB_08 Datasheet - Page 36

• Manufacturer Part Number: DP83848YB_08
• Manufacturer: NSC [National Semiconductor]

www.national.com
reading the upper byte of the MISR. One or more bits in the
MISR will be set, denoting all currently pending interrupts.
Reading of the MISR clears ALL pending interrupts.
Example: To generate an interrupt on a change of link sta-
tus or on a change of energy detect power state, the steps
would be:
— Write 0003h to MICR to set INTEN and INT_OE
— Write 0060h to MISR to set ED_INT_EN and
— Monitor PWR_DOWN/INT pin
When PWR_DOWN/INT pin asserts low, user would read
the MISR register to see if the ED_INT or LINK_INT bits
are set, i.e. which source caused the interrupt. After read-
ing the MISR, the interrupt bits should clear and the
PWR_DOWN/INT pin will deassert.
5.6 Energy Detect Mode
When Energy Detect is enabled and there is no activity on
the cable, the DP83848YB will remain in a low power mode
while monitoring the transmission line. Activity on the line
LINK_INT_EN
Figure 14. Top View, Thermal Vias for GNDPAD, pin 49.
36
will cause the DP83848YB to go through a normal power
up sequence. Regardless of cable activity, the DP83848YB
will occasionally wake up the transmitter to put ED pulses
on the line, but will otherwise draw as little power as possi-
ble. Energy detect functionality is controlled via register
Energy Detect Control (EDCR), address 0x1Dh.
5.7 Thermal Vias Recommendation
The following thermal via guidelines apply to GNDPAD, pin
49:
Adherence to this guideline is required to achieve the
intended operating temperature range of the device.
Figure 14 illustrates an example layout.
1. Thermal via size = 0.2 mm
2. Recommend 4 vias
3. Vias have a center to center separation of 2 mm.