PIC18C658 MICROCHIP [Microchip Technology], PIC18C658 Datasheet - Page 151
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PIC18C658
Manufacturer Part Number
PIC18C658
Description
High-Performance Microcontrollers with CAN Module
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18C658.pdf
(366 pages)
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15.4.3
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge Transmit
• Repeated START condition
FIGURE 15-10: MSSP BLOCK DIAGRAM (I
2000 Microchip Technology Inc.
SDA
SCL
Note:
MASTER MODE
I/O pins have diode protection to V
2
C bus may be taken when the
SDA In
Bus Collision
SCL In
Read
Advanced Information
DD
MSb
START bit, STOP bit,
Write Collision Detect
and V
End of XMIT/RCV
START bit Detect
State Counter for
Clock Arbitration
STOP bit Detect
Acknowledge
2
Generate
SSPBUF
SSPSR
C MASTER MODE)
SS
.
LSb
Write
15.4.4
Master mode is enabled by setting and clearing the
appropriate SSPM bits in SSPCON1 and by setting the
SSPEN bit. Once Master mode is enabled, the user
has the following six options:
1.
2.
3.
4.
5.
6.
Clock
Data Bus
Shift
Note:
Internal
Assert a START condition on SDA and SCL.
Assert a Repeated START condition on SDA
and SCL.
Write to the SSPBUF register initiating transmis-
sion of data/address.
Generate a STOP condition on SDA and SCL.
Configure the I
Generate an Acknowledge condition at the end
of a received byte of data.
Set/Reset, S, P, WCOL (SSPSTAT)
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
I
2
C MASTER MODE SUPPORT
The MSSP module, when configured in I
Master mode, does not allow queueing of
events. For instance, the user is not
allowed to initiate a START condition and
immediately write the SSPBUF register to
imitate transmission before the START
condition is complete. In this case, the
SSPBUF will not be written to and the
WCOL bit will be set, indicating that a write
to the SSPBUF did not occur.
2
C port to receive data.
PIC18CXX8
SSPADD<6:0>
SSPM3:SSPM0
Baud
Rate
Generator
DS30475A-page 151
2
C
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