MC68HC11A1 MOTOROLA [Motorola, Inc], MC68HC11A1 Datasheet - Page 12

• Manufacturer Part Number: MC68HC11A1
• Description: 8-Bit Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

TEST1 — Factory Test
TILOP — Test Illegal Opcode
OCCR — Output Condition Code Register to Timer Port
CBYP — Timer Divider Chain Bypass
DISR — Disable Resets from COP and Clock Monitor
FCM — Force Clock Monitor Failure
FCOP — Force COP Watchdog Failure
TCON — Test Configuration Register
CONFIG — COP, ROM, EEPROM Enables
NOSEC — EEPROM Security Disable
NOCOP — COP System Disable
ROMON — ROM Enable
EEON — EEPROM Enable
12
MOTOROLA
RESET:
RESET:
Test Modes Only
DISR is forced to one out of reset in special test and bootstrap modes.
Refer to 4 Electrically Erasable Programmable Read-Only Memory (EEPROM) .
Refer to 3 Resets and Interrupts .
In single-chip mode, ROMON is forced to one out of reset.
0 = 8K ROM removed from the memory map
1 = 8K ROM present in the memory map
0 = EEPROM is removed from the memory map
1 = EEPROM is present in the memory map
TILOP
Bit 7
Bit 7
0
0
0
The bits of this register are implemented with EEPROM cells. Programming and
erasing follow normal EEPROM procedures. The erased state of CONFIG is $0F.
A new value is not readable until after a subsequent reset sequence. CONFIG can
only be programmed or erased in special modes.
6
0
0
6
0
0
OCCR
5
0
5
0
0
CBYP
4
0
4
0
0
NOSEC
NOTE
DISR
—
—
3
3
NOCOP ROMON
FCM
—
2
0
2
FCOP
—
1
0
1
$103E
$103F
TCON
EEON
Bit 0
Bit 0
—
0
MC68HC11A8TS/D
MC68HC11A8