PIC18F1220 MICROCHIP [Microchip Technology], PIC18F1220 Datasheet - Page 210

• Manufacturer Part Number: PIC18F1220
• Description: 18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers with 10-bit A/D and nanoWatt Technology
• Manufacturer: MICROCHIP [Microchip Technology]

PIC18F1220/1320
COMF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39605C-page 208
Q Cycle Activity:
Before Instruction
After Instruction
Decode
REG
REG
W
Q1
=
=
=
register ‘f’
Complement f
[ label ] COMF
0
d
a
(f)
N, Z
The contents of register ‘f’ are
complemented. If ‘d’ is ‘0’, the
result is stored in W. If ‘d’ is ‘1’, the
result is stored back in register ‘f’
(default). If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1
COMF
Read
0001
Q2
0x13
0x13
0xEC
f
[0,1]
[0,1]
dest
255
11da
REG, W
Process
Data
Q3
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
CPFSEQ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC Address
W
REG
If REG
If REG
Q1
Q1
Q1
No
No
No
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, skip if f = W
[ label ] CPFSEQ
0
a
(f) – (W),
skip if (f) = (W)
(unsigned comparison)
None
Compares the contents of data
memory location ‘f’ to the contents
of W by performing an unsigned
subtraction.
If ‘f’ = W
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected,
overriding the BSR value. If ‘a’ = 1,
then the bank will be selected as
per the BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NEQUAL
EQUAL
Read
0110
Q2
Q2
Q2
No
No
No
=
=
=
=
=
=
f
[0,1]
 2004 Microchip Technology Inc.
255
by a 2-word instruction.
HERE
?
?
W;
Address (EQUAL)
W;
Address (NEQUAL)
,
then the fetched
CPFSEQ REG
:
:
001a
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
ffff
f [,a]
operation
operation
operation
operation
Q4
No
Q4
Q4
No
No
No
ffff