PLDC20RA10-15JC CYPRESS [Cypress Semiconductor], PLDC20RA10-15JC Datasheet
PLDC20RA10-15JC
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PLDC20RA10-15JC Summary of contents
Page 1
... CMOS manufacturing technology. The PLDC20RA10 is packaged pin 300-mil molded DIP, a 300-mil windowed cerDIP, and a 28-lead square lead- less chip carrier, providing inputs and 10 outputs. When the windowed device is exposed to UV light, the 20RA10 is erased and can then be reprogrammed ...
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... Note: 1. The CG7C324 is the PLDC20RA10 packaged in the JEDEC-compatible 28-pin PLCC pinout. Pin function and pin order is identical for both PLCC pinouts. The principal difference is in the location of the “no connect” (NC) pins Document #: 38-03012 Rev. ** ...
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... Output Always Enabled External Pin OE Figure 2. Four Possible Output Enable Alternatives for the PLDC20RA10 Document #: 38-03012 Rev. ** PRELOAD (FROM PIN Figure 1. PLDC20RA10 Macrocell RA10–6 Combination of Programmable and Hardwired RA10–8 PLDC20RA10 OUTPUT ENABLE (FROM PIN 13) ...
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... Registered/ActiveLOW Registered/Active HIGH Figure 3. Four Possible Macrocell Configurations for the PLDC20RA10 Document #: 38-03012 Rev RA10–10 RA10–12 PLDC20RA10 Combinatorial/Active LOW RA10–11 Combinatorial/Active HIGH RA10–13 Page ...
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... V = Max GND Outputs Open Max., Outputs Disabled (In High Z CC State) Device Operating at f MAX Test Conditions MHz 2 MHz OUT PLDC20RA10 Ambient Temperature + 10% – +125 C 5V 10% Min. Max. Unit Com’l 2.4 V Mil ...
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... RA10–16 Output W aveform Measurement Level V OH 0. 0. 0.5V (c) PLDC20RA10 ALL INPUT PULSES 3.0V 90% 10% < THÉ VENIN EQUIVALENT(Military) 190 2.02V=V OUTPUT V X RA10– RA10– RA10– RA10– RA10– RA10– ...
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... EA ER PZX PXZ PLDC20RA10 Military –20 –25 –35 Max. Min. Max. Min. Max 25.0 18.1 ...
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... ASYNCHRONOUS RESET OUTPUT Asynchronous Set ASYNCHRONOUS SET OUTPUT Document #: 38-03012 Rev SUP ARW ASW t S PLDC20RA10 RA10–26 RA10–27 RA10–28 RA10–29 Page ...
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... Functional Logic Diagram Document #: 38-03012 Rev. ** PLDC20RA10 Page ...
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... Ordering Information (ns) (ns) (ns) CC2 PLDC20RA10-15JC PLDC20RA10-15PC CG7C324-A15JC PLDC20RA10-20PC CG7C324-A20JC PLDC20RA10-20DMB PLDC20RA10-20WMB PLDC20RA10-25DMB PLDC20RA10-25WMB PLDC20RA10-35DMB PLDC20RA10-35WMB MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameter Subgroups ...
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... Package Diagrams 24-Lead (300-Mil) CerDIP D14 MIL-STD-1835 D- 9Config.A 28-Square L64 Carrier Chip MIL-STD-1835 C-4 Document #: 38-03012 Rev. ** 28-Lead Plastic Leaded Chip Carrier J64 Leadless 28-Pin Windowed Leadless Chip Carrier Q64 PLDC20RA10 MIL-STD-1835 C-4 Page ...
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... Package Diagrams (continued) Document #: 38-03012 Rev. ** 28-Pin Windowed Leaded Chip Carrier H64 PLDC20RA10 Page ...
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... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead (300-Mil) Windowed CerDIP W14 MIL-STD-1835 D- 9 Config.A PLDC20RA10 Page ...
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... Document Title: PLDC20RA10 Reprogrammable Asynchronous CMOS Logic Device Document Number: 38-03012 REV. ECN NO. Issue Date ** 106294 04/24/01 Document #: 38-03012 Rev. ** Orig. of Change SZV Change from Spec number: 38-00073 to 38-03012 PLDC20RA10 Description of Change Page ...