PLDC20RA10-15JC CYPRESS [Cypress Semiconductor], PLDC20RA10-15JC Datasheet - Page 7

• Manufacturer Part Number: PLDC20RA10-15JC
• Description: Reprogrammable Asynchronous CMOS Logic Device
• Manufacturer: CYPRESS [Cypress Semiconductor]

Switching Characteristics
Document #: 38-03012 Rev. **
t
t
t
t
t
t
t
t
t
t
t
f
t
t
t
t
t
t
t
t
Notes:
PD
EA
ER
PZX
PXZ
CO
SU
H
P
WH
WL
MAX
S
R
ARW
ASW
AR
WP
SUP
HP
7.
8.
Parameter
Part (a) of AC Test Loads was used for all parameters except t
The parameters t
+0.5V for an enabled LOW output. Please see part (c) of AC Test Loads and Waveforms for waveforms and measurement reference levels.
Input or Feedback to
Non-Registered Output
Input to Output Enable
Input to Output
Disable
Pin 13 to Output
Enable
Pin 13 to Output
Disable
Clock to Output
Input or Feedback
Set-Up Time
Hold Time
Clock Period
(t
Clock Width HIGH
Clock Width LOW
Maximum Frequency
(1/t
Input of Asynchronous
Set to Registered Output
Input of Asynchronous
Reset to Registered
Output
Asynchronous Reset
Width
Asynchronous S-Width
Asynchronous Set/
Reset Recovery Time
Preload Pulse Width
Preload Set-Up Time
Preload Hold Time
SU
ER
P
+ t
)
and t
[5]
[5]
Description
CO)
PXZ
are measured as the delay from the input disable logic threshold transition to V
[5]
Over the Operating Range
[5]
[5]
Min.
45.5
22
10
10
15
15
10
15
15
15
7
3
–15
Commercial
Max.
15
15
15
12
12
15
15
15
EA
, t
ER
, t
Min.
33.3
10
30
13
13
20
20
12
15
15
15
PZX
[3, 7, 8]
5
–20
and t
Max.
PXZ
20
20
20
15
15
20
20
20
, which use part (b).
Min.
33.3
10
30
12
12
20
20
12
15
15
15
3
–20
Max.
20
20
20
15
15
20
20
20
OH
Min.
25.0
15
40
18
18
25
25
15
15
15
15
5
- 0.5 V for an enabled HIGH output or V
Military
–25
Max.
25
30
30
20
20
25
25
25
PLDC20RA10
Min.
18.1
20
55
25
25
25
25
20
15
15
15
5
–35
Max.
35
35
35
25
25
35
40
40
Page 7 of 14
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OL