PCM3793RHB BURR-BROWN [Burr-Brown Corporation], PCM3793RHB Datasheet - Page 19

• Manufacturer Part Number: PCM3793RHB
• Description: 16-Bit, Low-Power Stereo Audio CODEC With Microphone Bias, Headphone, and Digital Speaker Amplifier
• Manufacturer: BURR-BROWN [Burr-Brown Corporation]

Power-On Reset and System Reset
The power-on-reset circuit outputs a reset signal, typically at V
the voltage of other power supplies (V
are removed from all analog and digital outputs. The PCM3793/94 does not require any power supply
sequencing. Register data must be written after turning all power supplies on.
System reset is enabled by setting register 85 (SRST), and all register are cleared automatically. All circuits are
reset to their default status at once. Note that the PCM3793/94 has audible pop noise on the analog outputs
when enabling SRST.
Power On/Off Sequence
To reduce audible pop noise, a sequence of register settings is required after turning all power supplies on when
powering up, or before turning the power supplies off when powering down. If some modules are not required for
a particular application or operation, they should be placed in the power-down state after performing the
power-on sequence. The recommended power-on and power-off sequences are shown in
respectively.
(1) Power supply sequencing is not required. It is recommended to set register data with system clock input after turning all power supplies
(2) Any level is acceptable for volume or attenuation. Level should be resumed by register data recorded when system power off.
(3) Audio interface format should be set to match the DSP or decoder being used.
www.ti.com
on.
STEP
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
System-clock pulse duration, high
System-clock pulse duration, low
REGISTER
SETTINGS
4BC0h
5A10h
49E0h
49FCh
4027h
4127h
4227h
4327h
4427h
4527h
4620h
5102h
5601h
4803h
5811h
–
SCKI
PARAMETERS
Turn on all power supplies
Headphone amplifier L-ch volume (–6 dB)
Headphone amplifier R-ch volume (–6 dB)
Speaker amplifier L-ch volume (–6 dB)
Speaker amplifier R-ch volume (–6 dB)
Digital attenuator L-ch (–24 dB)
Digital attenuator R-ch (–24 dB)
DAC audio interface format (left-justified)
Headphone detection enable and inverting polarity. Short and thermal detection enable
ADC audio interface format (left-justified)
V
DAC (DAL, DAR) and analog bias power up
Zero-cross detection enable
Analog mixer (MXL, MXR) power up
Analog mixer input (SW2, SW5) select
Headphone amplifier (HPL, HPR, HPC) power up
COM
Table 2. Recommended Power-On Sequence
ramp up/down time control. PG1, PG2 gain control (0 dB)
CC
Figure 25. System Clock Timing
, V
Submit Documentation Feedback
PA
and V
t
w(SCKL)
(1)
IO
). Internal circuits are cleared to default status, then signals
(2)
(2)
t
w(SCKH)
(2)
SYMBOL
(2)
t
t
w(SCKH)
w(SCKL)
(3)
(3)
(2)
(2)
DD
= 1.2 V, and this circuit does not depend on
NOTE
SLES193A – AUGUST 2006 – REVISED SEPTEMBER 2006
MIN
7
7
0.7 V
0.3 V
T0005-12
IO
IO
Table 2
UNITS
and
PCM3793
PCM3794
ns
ns
Table
19
3,