PALCE22V10 LATTICE [Lattice Semiconductor], PALCE22V10 Datasheet - Page 31

• Manufacturer Part Number: PALCE22V10
• Description: 24-Pin EE CMOS (Zero Power) Versatile PAL Device
• Manufacturer: LATTICE [Lattice Semiconductor]

POWER-UP RESET
The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been
powered up. The output state will depend on the programmed pattern. This feature is valuable in
simplifying state machine initialization. A timing diagram and parameter table are shown below.
Due to the synchronous operation of the power-up reset and the wide range of ways V
to its steady state, two conditions are required to ensure a valid power-up reset. These conditions
are:
t
t
t
PR
S
WL
The V
Following reset, the clock input must not be driven from LOW to HIGH until all applicable input
and feedback setup times are met.
Parameter
Active-Low
Registered
Symbol
Power
Output
Clock
CC
rise must be monotonic.
Power-up Reset Time
Input or Feedback Setup Time
Clock Width LOW
4 V
Parameter Description
PALCE22V10 and PALCE22V10Z Families
V CC Off
Figure 3. Power-Up Reset Waveform
t PR
t
WL
t S
Max
1000
Characteristics
See Switching
V CC
CC
Unit
ns
can rise
16564E-021
31