ISP1563BM PHILIPS [NXP Semiconductors], ISP1563BM Datasheet - Page 77

• Manufacturer Part Number: ISP1563BM
• Description: Hi-Speed Universal Serial Bus PCI Host Controller
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 104: USBSTS - USB Status register bit allocation
Address: Value read from func2 of address 10h + 24h
[1]
9397 750 14224
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
The reserved bits should always be written with the reset value.
ASS
R/W
R/W
R/W
31
23
15
R
0
0
0
7
0
reserved
Table 105: USBSTS - USB Status register bit description
Address: Value read from func2 of address 10h + 24h
Bit
31 to 16 reserved
15
14
13
12
PSSTAT
[1]
R/W
R/W
R/W
30
22
14
R
0
0
0
6
0
Symbol
ASS
PSSTAT
RECL
HCH
RECL
R/W
R/W
IAA
29
21
13
R
R
0
0
0
5
0
Rev. 01 — 14 July 2005
Description
-
Asynchronous Schedule Status: Default = 0. The bit reports the
current real status of the asynchronous schedule. If this bit is logic 0,
the status of the asynchronous schedule is disabled. If this bit is logic 1,
the status of the asynchronous schedule is enabled. The Host
Controller is not required to immediately disable or enable the
asynchronous schedule when software changes ASE (bit 5 in the
USBCMD register). When this bit and the ASE bit have the same value,
the asynchronous schedule is either enabled (1) or disabled (0).
Periodic Schedule Status: Default = 0. This bit reports the current
status of the periodic schedule. If this bit is logic 0, the status of the
periodic schedule is disabled. If this bit is logic 1, the status of the
periodic schedule is enabled. The Host Controller is not required to
immediately disable or enable the periodic schedule when software
changes PSE (bit 4 in the USBCMD register). When this bit and the
PSE bit have the same value, the periodic schedule is either enabled (1)
or disabled (0).
Reclamation: Default = 0. This is a read-only status bit that is used to
detect an empty asynchronous schedule.
HCHalted: Default = 1. This bit is logic 0 when RS (bit 0 of the
USBCMD register) is logic 1. The Host Controller sets this bit to logic 1
after it has stopped executing because the RS bit is set to logic 0, either
by software or by the Host Controller hardware. For example, on an
internal error.
HCH
HSE
R/W
R/W
R/W
28
20
12
R
0
0
1
4
0
reserved
reserved
[1]
[1]
R/W
R/W
R/W
R/W
FLR
27
19
11
0
0
0
3
0
PCD
R/W
R/W
R/W
R/W
26
18
10
0
0
0
2
0
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
reserved
USBERRIN
[1]
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
T
0
ISP1563
USBINT
R/W
R/W
R/W
R/W
77 of 107
24
16
0
0
8
0
0
0