PIC18F24J50 MICROCHIP [Microchip Technology], PIC18F24J50 Datasheet - Page 3

• Manufacturer Part Number: PIC18F24J50
• Description: PIC18F46J50 Family Silicon Errata and Data Sheet Clarification
• Manufacturer: MICROCHIP [Microchip Technology]

Silicon Errata Issues
1. Module: Master Synchronous Serial Port
 2010 Microchip Technology Inc.
Note:
If the LATB<5> or LATB<4> bit is set, the
MSSP1 module will not work correctly in the
I
are clear, the module will work normally.
Work around
Clear the bits, LATB<5:4>, prior to enabling the
MSSP1 module in an I
clear while using the module.
For operation in I
bits should be set.
Affected Silicon Revisions
2
C™ modes. If both LATB<5> and LATB<4>
A2
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (Rev. A4).
A4
(MSSP1)
2
C modes, the TRISB<5:4>
2
C mode. Keep these bits
PIC18F46J50 FAMILY
2. Module: Master Synchronous Serial Port
In extremely rare cases, when configured for I
slave reception, the MSSP module may not receive
the correct data. This occurs only if the Serial
Receive/Transmit Buffer Register (SSPxBUF) is not
read within a window after the SSPxIF interrupt
has occurred.
Work around
The issue can be resolved in either of these ways:
• Prior to the I
• Each time the SSPxIF is set, read the
Affected Silicon Revisions
A2
clock stretching feature.
This
(SSPxCON2<0>).
SSPxBUF before the first rising clock edge of
the next byte being received.
X
A4
X
is
(MSSP)
done
2
C slave reception, enable the
by
setting
DS80436C-page 3
the
SEN
2
C™
bit