MC68HC705SR3 MOTOROLA [Motorola, Inc], MC68HC705SR3 Datasheet - Page 43

• Manufacturer Part Number: MC68HC705SR3
• Description: High-density Complementary Metal Oxide Semiconductor (HCMOS) Microcontroller Units
• Manufacturer: MOTOROLA [Motorola, Inc]

5.2.2.2
The port pin PD6 is configured as IRQ2 by setting the IRQ2E bit in the MCR. The external interrupt
IRQ2 behaves similar to IRQ except it is edge-triggered only.
IRQ2E — IRQ2 Enable
IRQ2F — IRQ2 Flag clear
This is a write-only bit and always read as “0”.
When a negative-edge is sensed on IRQ2 pin, an external interrupt occurs. The actual processor
interrupt is generated only if the I-bit in the CCR is also cleared. When the interrupt is recognized,
the current state of the processor is pushed onto the stack and the I-bit in the CCR is set. This
masks further interrupts until the present one is serviced. The latch for IRQ2 is cleared by reset or
by writing a “1” to the IRQ2F bit in the MCR in the interrupt service routine. The interrupt service
routine address is specified by the contents in $1FF8-$1FF9.
5.2.2.3
The timer interrupt is generated by the 8-bit timer when a timer overflow has occurred. The
interrupt enable and flag for the timer interrupt are located in the Timer Control Register.
TIM — Timer Interrupt Mask
MC68HC05SR3
Miscellaneous Control Register
Timer Control Register (TCR)
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
External Interrupt 2 (IRQ2)
Timer Interrupt
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External interrupt IRQ2 is enabled.
External interrupt IRQ2 is disabled.
Writing a “1” clears the IRQ2 interrupt latch.
Writing a “0” has no effect.
Timer interrupt is disabled.
Timer interrupt is enabled.
Address bit 7
Address bit 7
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$0C
$09
RESETS AND INTERRUPTS
KBIE
TIF
KBIC
bit 6
bit 6
TIM
TCEX
INTO
bit 5
bit 5
INTE
TINE
bit 4
bit 4
PREP
LVRE
bit 3
bit 3
bit 2
bit 2
PR2
SM
IRQ2F IRQ2E 0001 0000
bit 1
bit 1
PR1
bit 0
bit 0
PR0
MOTOROLA
0100 -100
on reset
on reset
State
State
TPG
5-7
5