MC33099CDW FREESCALE [Freescale Semiconductor, Inc], MC33099CDW Datasheet - Page 15

• Manufacturer Part Number: MC33099CDW
• Description: Adaptive Alternator Voltage Regulator
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

circuitry to limit the lamp drive and regulates the lamp current
to current I
causes the temperature of the lamp driver to exceed a
thermal shut-down temperature limit (T
sensing diode (D
a signal to the lamp driver circuitry to limit the lamp drive
current and reduce the power dissipation and resulting
device temperature. When the lamp driver is ON, but the
Lamp Drain pin voltage is not below the BAT pin voltage V
by at least a lamp drain short circuit threshold voltage (V
or ([V
short circuit signal to the Drain Polling circuit to indicate a
lamp shorted condition. The Drain Polling circuit provides a
low duty cycle polling output to the input of the AND2 GATE
to poll the lamp driver ON, continuously testing for a lamp
short without damaging the lamp driver. The polling duty
cycle is 1.56%, (or about a 158 µs ON pulse) at a frequency
of f
the comparator C
Drain Polling circuitry, which provides a logic [1] to the AND2
GATE, which then operates normally.
case, lamp polling turns OFF the lamp for a short period of
time with the lamp being ON for the remainder of the time. In
this case the lamp ON duty cycle is 98.44% (or OFF for
158 µs) at a frequency of f
lamp voltage on the lamp drain pin to be greater than ignition
threshold voltage V
period. During the lamp ON mode, the Ignition Turn Off Delay
of the Ignition Delay circuit is greater then the 10.1 ms period.
As a result, the regulator biasing remains ON even when the
IGN pin is coupled to the LAMP DRAIN pin and the lamp
drain voltage is less than voltage V
the lamp is ON.
during load dump, the
AND2 GATE from activating the lamp driver. In addition, a
drain-to-GATE clamp device Z2 limits the drain-to-GATE
clamping voltage (V
UNDERVOLTAGE, OVERVOLTAGE, AND LOAD
DUMP PROTECTION
sensed by the regulator to generate fault indications and to
Analog Integrated Circuit Device Data
Freescale Semiconductor
Lamp polling is also present when the lamp is ON. In this
The lamp driver is also protected from load dump, since
An undervoltage, overvoltage and load dump condition is
msb
bat
/4, or 98.6 Hz. After the lamp short has been removed,
- V
dsc
drain
. When the power dissipation of the lamp driver
] < V
tl
ds
) causes the thermal limit circuitry to send
Tign
dg
outputs a lamp not-shorted signal to the
Tdsc
) to about 40 V typically.
LD
for at least 158 µs of a 10.1 ms
), comparator C
msb
signal is a logic [0], preventing the
/4, or 98.6 Hz. This causes the
Tig
n
most of the time when
Lim
ds
), a temperature
will output a lamp
Tdsc
bat
)
protect the regulator and associated external devices. As
previously discussed, a load dump signal during load dump
will prevent GATE drive to the external MOSFET and prevent
GATE drive to the lamp driver. Thus the external and internal
MOSFETs will turn OFF during a system load dump. As
previously discussed, the undervoltage and overvoltage
signals are also provided for fault indications.
undervoltage comparator C
1.25 V and a resistor divider voltage transfer of 1.26 from the
FB output to comparator C
FB output becomes less than 1.52 V, the voltage at input to
comparator C
comparator C
Because voltage V
and the ratio of V
occur when the system voltage at the Remote input (or Local
input) is less than an undervoltage threshold voltage (V
or 11.35 V. However, GATE AND1 ensures that frequency
f
indicated by the lamp.
similar resistor dividers and voltage comparators in an
Overvoltage Detect circuitry where all comparators are
referenced to voltage V
on the FB output is greater than 2.58 V, or 1.29 V
on the
will be about 2.58 V, and the actual load dump threshold
voltage (V
voltage V
the OV line. Thus voltage V
and the actual overvoltage threshold voltage (V
about 16.65 V, or 1.125 V
the system during the Remote fault condition when the
remote wire resistance increases to a finite value and the
system voltage is being regulated by secondary regulation at
V
regulation, the load dump threshold increases to 1.3 V
about 24 V.
= 1.29), an output load dump signal of a logic [0] is generated
V
ph
set2
ref
The undervoltage signal is provided on the UV line by an
The load dump and overvoltage detection also utilizes
The regulator also indicates an overvoltage condition on
must be greater than f
= 1.117), an output overvoltage signal is generated on
. When a load dump occurs during secondary
LD
fb
line. Thus during load dump, voltage V
Tld
on the FB output is greater than 1.117 V
) will be about 19.25 V, or 1.3 V
uv
uv
becomes less than 1.25 V, causing
to output an undervoltage UV signal.
r
/ V
fb
rs
is ideally voltage V
(or V
ref
2
, or about 2.0 V. When voltage V
set
uv
before an undervoltage Fault is
uv
l
rs
/ V
.
input. When voltage V
(or V
having a voltage reference of
ls
) is 7.45, the UV signal will
l
) will be about 2.235 V,
TYPICAL APPLICATIONS
rs
(or voltage V
set
. When
Tov
rs
ref
(or V
) will be
(V
fb
ref
set2
fb
on the
Tuv
local
(V
ls
/ V
33099
),
, or
fb
ref
15
fb
),
)
/