PIC18F2510 MICROCHIP [Microchip Technology], PIC18F2510 Datasheet - Page 273
PIC18F2510
Manufacturer Part Number
PIC18F2510
Description
28/40/44-PIN FLASH MICROCONTROLLERS WITH 10-BIT A/D AND NANO WATT TECHNOLOGY
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2510.pdf
(380 pages)
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BTG
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction:
After Instruction:
Decode
PORTC =
PORTC =
Q1
register ‘f’
BTG
Bit Toggle f
BTG f, b {,a}
0
0
a
(f<b>)
None
Bit ‘b’ in data memory location ‘f’ is
inverted.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
Section 23.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1
Read
0111
Q2
f
b < 7
0111 0101 [75h]
0110 0101 [65h]
[0,1]
255
f<b>
PORTC,
bbba
Process
Data
Q3
95 (5Fh). See
4, 0
ffff
register ‘f’
Write
Q4
ffff
Preliminary
BOV
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
PIC18F2X1X/4X1X
Decode
Decode
No
PC
If Overflow
If Overflow
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Overflow
BOV
-128
if Overflow bit is ‘1’
(PC) + 2 + 2n
None
If the Overflow bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
No
Q2
‘n’
Q2
‘n’
=
=
=
=
=
n
n
address (HERE)
1;
address (Jump)
0;
address (HERE + 2)
127
0100
BOV
operation
Process
Process
Data
Data
No
PC
Q3
Q3
DS39636A-page 271
Jump
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn
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