MC68HC708XL36 FREESCALE [Freescale Semiconductor, Inc], MC68HC708XL36 Datasheet - Page 213

• Manufacturer Part Number: MC68HC708XL36
• Description: HCMOS Microcontroller Unit
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Queuing Transmission Data
13-spi_c
MOTOROLA
(CPHA:CPOL = 1:0)
WRITE TO SPDR
4 FIRST INCOMING BYTE TRANSFERS FROM SHIFT
5
1
2
3
6 CPU READS SPSCR WITH SPRF BIT SET.
READ SPSCR
CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.
BYTE 1 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2
AND CLEARING SPTE BIT.
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 2 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
READ SPDR
SPSCK
SPTE
SPRF
MOSI
The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high.
associated with doing back-to-back transmissions with the SPI (SPSCK
has CPHA:CPOL = 1:0).
The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.
1
Figure 8. SPRF/SPTE CPU Interrupt Timing
Freescale Semiconductor, Inc.
For More Information On This Product,
MSB BIT
BYTE 1
2
Go to: www.freescale.com
6
BIT
5
3
BIT
4
BIT
3
SPI
BIT
2
BIT
1
10
11 CPU READS SPSCR WITH SPRF BIT SET.
12 CPU READS SPDR, CLEARING SPRF BIT.
7 CPU READS SPDR, CLEARING SPRF BIT.
8
9
LSB MSB BIT
5
4
CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE
3 AND CLEARING SPTE BIT.
SECOND INCOMING BYTE TRANSFERS FROM SHIFT
REGISTER TO RECEIVE DATA REGISTER, SETTING
SPRF BIT.
BYTE 3 TRANSFERS FROM TRANSMIT DATA
REGISTER TO SHIFT REGISTER, SETTING SPTE BIT.
BYTE 2
6
6
7
BIT
5
8
BIT
4
BIT
3
BIT
2
BIT
Figure 8
1
LSB MSB BIT
10
9
Queuing Transmission Data
BYTE 3
11
6
12
shows the timing
BIT
5
MC68HC708XL36
BIT
4
213
SPI