LAN83C180_01 SMSC [SMSC Corporation], LAN83C180_01 Datasheet - Page 13

• Manufacturer Part Number: LAN83C180_01
• Description: 10/100 Fast Ethernet PHY Transceiver
• Manufacturer: SMSC [SMSC Corporation]

MANAGEMENT
MAC Access to PHY Management Registers
The interface to these registers is via the MDC and MDIO signals. The address of the LAN83C180 is
specified by the PA<4:0> static inputs. The MD command is issued by the MAC and can be read or write:
RESISTER SET
The following register set is implemented in the LAN83C180 device. Each of the registers is accessible to the MAC
at the specified offset. The bit types in the bit description tables follow the following convention:
SC = Self clear
RO = Read only
RW = Read or write
LL = Latch low until register read
LH = Latch high until register read
Res = Reserved
Reg 0 - Control Register
SMSC DS – LAN83C180
COMMAND
BIT
6:0
15
14
13
12
11
10
WRITE
9
8
7
READ
Duplex Selection
Speed Selection
Restart ANEG
ANEG Enable
Collision Test
Power Down
BIT NAME
Loopback
Reserved
Isolation
PREAMBLE
32 Bits of 1
32 Bits of 1
Reset
START
1 = PHY reset
0 = Normal operation
1 = Loopback mode active
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
1 = Enable ANEG process
0 = Disable ANEG process
1 = Power down active
0 = Normal operation
1 = Isolation in process
0 = Normal operation
1 = Restart the ANEG process
0 = Normal operation
1= Full Duplex mode
0 = Half duplex mode
1 = Collision test active
0 = Normal operation
Write as 0; ignore on read
DATA
01b
01b
CODE
DESCRIPTION
10b
01b
OP
Page 13
ADDRESS
5 Bits
5 Bits
PHY
NUMBER
5 Bits
5 Bits
REG
DEFAULT
0
0
1
1
0
0
0
1
0
Z0b
10b
TA
16 bit from
PHY
16 bit from
MAC
DATA
TYPE
Rev. 08/24/2001
RW
RW
RW
RW
RW
RW
RW
RW
RW
SC
SC