LAN91C100-FD SMSC [SMSC Corporation], LAN91C100-FD Datasheet - Page 57
LAN91C100-FD
Manufacturer Part Number
LAN91C100-FD
Description
FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
Manufacturer
SMSC [SMSC Corporation]
Datasheet
1.LAN91C100-FD.pdf
(79 pages)
- Current page: 57 of 79
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SMSC DS – LAN91C100FD Rev. D
FEAST Fast Ethernet Controller with Full Duplex Capability
nBE0 nBE1
nBE2 nBE3
VL BUS
SIGNAL
D0-D31
nLDEV
OPEN
nADS
IRQn
GND
VCC
nADS, nCYCLE
INTR0-INTR3
LAN91C100
A1 nVLBUS
nBE0 nBE1
nBE2 nBE3
nDATACS
nRD nWR
SIGNAL
D0-D31
nLDEV
PRELIMINARY
Byte enables. Latched transparently by nADS rising edge.
Address Strobe is connected directly to the VL bus. nCYCLE is
created typically by using nADS delayed by one LCLK.
Typically uses the interrupt lines on the ISA edge connector of
VL bus
32 bit data bus. The bus byte(s) used to access the device are a
function of nBE0-nBE3:
nBE0
Not used = tri-state on reads, ignored on writes. Note that nBE2
and nBE3 override the value of A1, which is tied low in this
application.
nLDEV is a totem pole output. nLDEV is active on valid decodes
of A15-A4 and AEN=0.
0
0
1
0
1
1
1
UNUSED PINS
nBE1
Page 57
0
0
1
1
0
1
1
nBE2
0
1
0
1
1
0
1
nBE3
NOTES
0
1
0
1
1
1
0
Double word access
Low word access
High word access
Byte 0 access
Byte 1 access
Byte 2 access
Byte 3 access
Rev. 10/14/2002
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