LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 50

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Rev. 03-28-07
A15
0
4 THROUGH 9
The I/O base decode defaults to 300h (namely, the high byte defaults to 18h). ROM SIZE defaults to 01.
ROM decode defaults to CC000 (namely the low byte defaults to 67h).
Below chart shows the decoding of I/O Base Address 300h:
I/O SPACE - BANK1
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or
EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not
modify the EEPROM Individual Address contents.
Bit 0 of Individual Address 0 register corresponds to the first bit of the address on the cable.
A14
OFFSET
0
0
0
0
0
0
0
A13
0
A12
0
0
0
0
0
0
0
INDIVIDUAL ADDRESS REGISTERS
A11
0
A10
0
0
0
0
0
0
0
DATASHEET
NAME
A9
1
ADDRESS 0
ADDRESS 1
ADDRESS 2
ADDRESS 3
ADDRESS 4
ADDRESS 5
0
0
0
0
0
0
A8
1
Page 50
Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
A7
0
0
0
0
0
0
0
A6
0
READ/WRITE
A5
0
0
0
0
0
0
0
TYPE
A4
0
0
0
0
0
0
0
A3
0
A2
SYMBOL
0
0
0
0
0
0
0
SMSC LAN91C965v&3v
IAR
A1
0
A0
0