LAN91C96_07 SMSC [SMSC Corporation], LAN91C96_07 Datasheet - Page 57

• Manufacturer Part Number: LAN91C96_07
• Description: Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
• Manufacturer: SMSC [SMSC Corporation]

Note:
SMSC LAN91C965v&3v
“For underrun detection purposes the RAM logical address and packet numbers of the packet being
loaded are compared against the logical address and packet numbers of the packet being transmitted. If
the packet numbers match and the logical address of the packet being transmitted exceeds the address
being loaded the LAN91C96 will prevent the transmission of erroneous data by forcing an Underrun
condition. Underruns will be triggered by starving the transmit DMA if the LAN91C96 detects that the DMA
TX address exceeds the pointer address.”
ETEN-TYPE (bit 14) in TCR may be implemented for Rev. ID 6 only. In the absence of ETEN-TYPE in
TCR, ETEN will have the definition as ETEN-TYPE were clear only.
AutoTx bit - When set, enables the transmit state machine to Automatically start a transmit operation with
no host intervention determined by the number of bytes being copied into the transmit buffer enqueued in
the transmit FIFO. The ETEN bit must also be set in order for this function to be enabled and the RCV bit
must be cleared (0). When the Auto TX bit is cleared, the transmit state machine must manually be
enabled to enqueue a transmit buffer.
If AUTO INCR. is not set, the pointer must be loaded with an even value.
I/O SPACE - BANK2
DATA REGISTER - Used to read or write the data buffer byte/word presently addressed by the pointer
register.
This register is mapped into two uni-directional FIFOs that allow moving words to and from the LAN91C96
regardless of whether the pointer address is even or odd. Data goes through the write FIFO into memory,
and is pre-fetched from memory into the read FIFO. If byte accesses are used, the appropriate (next) byte
can be accessed through the Data Low or Data High registers. The order to and from the FIFO is
preserved. Byte and word accesses can be mixed on the fly in any order.
This register is mapped into two consecutive word locations to facilitate the usage of double word move
instructions. The DATA register is accessible at any address in the 8 through Ah range, while the number
of bytes being transferred are determined by A0 and nSBHE in LOCAL BUS mode, and by A0, nCE1 and
nCE2 in PCMCIA mode.
OFFSET
8 & A
DATA REGISTER
DATASHEET
NAME
DATA HIGH
DATA LOW
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Non-PCI Single-Chip Full Duplex Ethernet Controller with Magic Packet
READ/WRITE
TYPE
SYMBOL
DATA
Rev. 03-28-07