LAN9215-MT-E2 SMSC [SMSC Corporation], LAN9215-MT-E2 Datasheet - Page 123

• Manufacturer Part Number: LAN9215-MT-E2
• Description: Highly Efficient 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

Highly Efficient Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC LAN9215
6.4
SYMBOL
t
t
t
t
cycle
t
t
t
csdv
t
t
csh
asu
don
doff
doh
csl
ah
FIFO_SEL
nCS, nRD
A[2:1]
Data Bus
In this mode the upper address inputs are not decoded, and any read of the LAN9215 will read the
RX Data FIFO. This mode is enabled when FIFO_SEL is driven high during a read access. This is
normally accomplished by connecting the FIFO_SEL signal to high-order address line. This mode is
useful when the host processor must increment its address when accessing the LAN9215 . Timing is
identical to a PIO read, and the FIFO_SEL signal has the same timing characteristics as the address
lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
Note: The “Data Bus” width is 16 bits
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The
RX Data FIFO Direct PIO Reads
DESCRIPTION
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time (see Note below)
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
cycle ends when either or both nCS and nRD are de-asserted. They may be asserted and de-
asserted in any order. Parameters t
t
cycle
minimum.
Figure 6.3 RX Data FIFO Direct PIO Read Cycle Timing
Table 6.5 RX Data FIFO Direct PIO Read Timing
DATASHEET
123
csh
and t
csl
must be extended using wait states to meet the
MIN
165
32
13
0
0
0
0
TYP
133
Revision 1.5 (07-18-06)
MAX
30
7
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns