PEB2080 SIEMENS [Siemens Semiconductor Group], PEB2080 Datasheet - Page 22

• Manufacturer Part Number: PEB2080
• Description: S/T Bus Interface Circuit(SBC)
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

IOM-1 Mode
This timing mode is applicable in all operating modes of the SBC.
Nominal bit rate of data (SDI and SDO):
Nominal frequency of DCL:
Nominal frequency of FSC:
Transitions of the data occur after even-numbered rising edges of DCL. Even-numbered rising
edges of the clock are defined as the second rising edge following the rising edge of FSC and every
second rising edge thereafter.
The frame is earmarked by the rising edge of FSC.
Figure 9
Timing of Data and Clocks of IOM
Inverted Mode
Timing mode applicable in TE mode: 512 kHz
The characteristics are the same as above, except that FSC is not a signal with 50 %, duty cyc!e
but an active low pulse, one DCL clock period long, which occurs in the middle of bit 27 (fourth bit
of B*).
Timing mode applicable in LT-T and LT-S operating modes: 4096 kHz
Nominal bit rate of data bursts (SDI and SDO)
Nominal frequency of DCL
Nominal frequency of FSC
The frame clock FSC is an active low strobe clock. The strobe earmarks the second half of bit
no. 251 in the frame. The low state of the strobe is detected with the rising edge of DCL. Refer to
figure 10.
The data at the input SDI is valid on the even-numbered rising edges of DCL. Transitions of the data
on SDO occur after even-numbered falling edges of DCL. The rising edge earmarked by the frame
strobe is an even-numbered rising edge of DCL. The following falling edge is an even-numbered
falling edge.
Semiconductor Group
®
in the Normal Mode
23
256 kbit/s
512 kHz
8 kHz
2048 kbit/s
4096 kHz
8 kHz.
Functional Description