TMC22151AKHC CADEKA [Cadeka Microcircuits LLC.], TMC22151AKHC Datasheet - Page 65

• Manufacturer Part Number: TMC22151AKHC
• Description: Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit
• Manufacturer: CADEKA [Cadeka Microcircuits LLC.]

PRODUCT SPECIFICATION
VINDO Operation
The VINDO circuit uses the line idents on LID
blanking signals to control the comb filter output and the
blanking of the YUV data in the output matrix during the
vertical blanking period.
The vertical window VINDO starts on the first line after the
last equalizing pulse, at LID
HIGH from this line until the VINDO count = VINDO
the VBLK signal goes HIGH, at which time the VINDO goes
LOW. While the VINDO is HIGH the decoder operation is
controlled by VDIV, and during the time the VINDO and
VBLK are LOW the decoder operation is controlled by
VDOV.
Table 22. PAL VINDO operation
NTSC VINDO operation
REV. 1.0.0 2/4/03
00 - 01
02 - 0A
02 - 0A
02 - 0A
02 - 0A
0B - 17
00 - 02
03 - 06
03 - 06
03 - 06
03 - 06
07 - 17
LID
LID
Video A
Video B
4-0
4-0
VINDO VDIV
VINDO
1
1
0
0
x
1
1
0
0
x
x
x
Luma and
Chroma
Separation
VDIV
0
1
x
x
x
x
x
0
1
x
x
x
Y Data
C Data
4-0
VDOV
Pixel
= 02. The VINDO stays
VDOV
x
x
x
0
1
x
0
1
x
x
x
x
Chroma
Demodulation
normal
normal
normal normal
normal normal
simple
simple
simple
simple
black
black
flat
flat
Y
Y
dT
Figure 32. Pixel Grab Locations
4-0
, and the
normal
normal
simple
simple
black
black
black
black
black
black
Luma
Proc
4-0
LPF
LPF
C
C
register 3A/3C
register 3B/3C
register 38/3C
register 39/3C
U Data
Grab
V Data
Grab
Y Data
Grab
MS Data
Grab
, or
MS
Y
U
V
Video Measurement
The TMC22x5yA supports a comprehensive set of video
measurement techniques to aid the user in setting up the
gain, phase, etc. of the decoder and in tracking down system
errors.
Pixel Grab
The pixel grab allows the user to grab one pixel every line,
or one pixel out of the four field sequence in NTSC or the 8
field sequence in PAL, under software control. The SET pin
can also be used to produce the pixel grab pulse if SET
110 and PGEXT is set HIGH.
The 10 bit G/Y, B/U, R/V outputs are stored in one set of
four 8 bit registers in the FORMAT block, while the 10 bit
luma and mixed sync data and the 10 bit demodulated U and
V color difference signals are stored in a set of five 8 bit
registers in the GRAB circuit block. The pixel grab signal,
PIXEL, whether internally or externally generated, is inter-
nally delayed to ensure that the all the grabbed data are from
the same pixel relative to the line sync pulse. The PIXEL
signal is equal to PGRAB or the logical AND of PGRAB
with FGRAB and LGRAB, and is controlled by the LPGEN,
PGEN, and PGEXT register bits.
The luma and mixed sync signals are multiplexed on the
YMS data bus and the U and V signals are multiplexed on
the UV data bus, at the PXCK clock rate. The pixel grab
signal accommodates for this when grabbing these
components.
An example of the pixel grab feature, is grabbing a pixel in
the center of the burst period allowing the user to check the
burst height by reading the magnitude of the demodulated U
and V components. This allows the user to compensate for
any chrominance gain errors in the output matrix.
YMS
UV
dT
Output
Matrix
register 34/37
register 35/37
register 36/37
G/Y
Grab
B/U
Grab
RV
Grab
and Buffer
Formatter
Output
65-22x5y-72
TMC22x5yA
G/Y
B/U
R/V
2-0
65
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