MCZ33784EF/R2- FREESCALE [Freescale Semiconductor, Inc], MCZ33784EF/R2- Datasheet - Page 17

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MCZ33784EF/R2-

Manufacturer Part Number
MCZ33784EF/R2-
Description
DSI 2.02 Sensor Interface
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
bus, the 33784 will calculate a CRC as each bit is received.
The CRC is calculated using the polynomial and seed that
have been programmed into the IC via the bus. At the
conclusion of the transmission, the 33784 will compare the
calculated CRC with the CRC included within the message. If
Table 7. Standard and Enhanced DBUS Command Structure
Table 8. Standard and Enhanced DBUS Response Structure
STANDARD DBUS RESPONSE STRUCTURE
with the two standard command word lengths. A standard
long response always consists of 16 data bits and 4 CRC bits.
A standard short response always consists of 8 data bits and
4 CRC bits. Refer to
MSB, and are followed by the CRC bits. The CRC bits are
calculated from the data bits using the standard polynomial
X
changed when responding in standard mode.
standard long commands, and standard short responses will
be sent for standard short commands. However, if a long
command is followed by a short command, then the response
to the long command will occur during the short command
and will be truncated. In this case, the response to the long
command is considered invalid.
command, then the response to the short command will occur
during the long command and will contain extra bits. In this
case the response to the short command is considered
invalid.
Analog Integrated Circuit Device Data
Freescale Semiconductor
10-Bit Enhanced Short Word 10-Bit ESW
10-Bit Enhanced Short Word 10-Bit ESW
8-Bit Enhanced Short Word
8-Bit Enhanced Short Word
4
+1 and seed 1010. The polynomial and seed cannot be
When an enhanced long word or short word is sent on the
There are two standard response lengths to correspond
In both cases, the data bits are sent first, starting with the
Normally, standard long responses will be sent for
Similarly, if a short command is followed by a long
Enhanced Long Word
Standard Short Word
Standard Long Word
Enhanced Long Word
Standard Short Word
Standard Long Word
Word Type
Word Type
Table
8-Bit ESW
Symbol
8-Bit ESW
Symbol
ELW
8.
SW
LW
ELW
LW
SW
First
D7
D7
D15
D15
First
D6
D6
D14
D14
D5
D5
D13
D13
D4
D4
D12
D12
Data
D3
D3
D11
D11
D2
D2
D10
D10
D1
D1
D1
the two match, the message is considered valid and the
33784 will act on the message accordingly. If the calculated
CRC does not match the CRC included within the message,
the 33784 will ignore the transmission and the message will
be discarded.
ENHANCED DBUS RESPONSE STRUCTURE
with the two enhanced command word lengths. Like the
standard long word, an enhanced long response always
consists of 16 data bits and 4 CRC bits. The data bits are sent
first, starting with the MSB, and are followed by the CRC bits.
The CRC bits are calculated from the data bits using the
polynomial and seed that was programmed into the IC via the
bus.
data bits and 4 CRC bits. The enhanced short response will
have 8 data bits if the enhanced short command did not use
the optional 2 bits, and it will have 10 data bits if the enhanced
short command did use the optional 2 bits.
command, but due to the nature of the command, the
response only contains 8 bits of data. In this circumstance,
the response will be right-padded with zeros so that 10 data
bits are sent, followed by the CRC.
command, but due to the nature of the command, the
response contains 10 bits of data. In this circumstance, the 2
least significant bits of the response data will be dropped and
only the 8 most significant data bits are sent, followed by the
CRC. This is illustrated in
page 18.
D9
D9
D9
D0
D0
D0
There are two enhanced response lengths to correspond
An enhanced short response consists of either 8 or 10
In certain cases, the optional 2 bits might be used in the
In other cases, the optional 2 bits might not be used in the
D8
D8
D8
Response
A3
A3
A3
A3
A3
D7
D7
D7
D7
D7
Address
A2
A2
A2
A2
A2
D6
D6
D6
D6
D6
A1
A1
A1
A1
A1
D5
D5
D5
D5
D5
A0
A0
A0
A0
A0
D4
D4
D4
D4
D4
C3
C3
C3
C3
C3
logic Commands and
FUNCTIONAL DEVICE OPERATION
D3
D3
D3
D3
D3
Command
C2
C2
C2
C2
C2
D2
D2
D2
D2
D2
C1
C1
C1
C1
C1
D1
D1
D1
D1
D1
OPERATIONAL MODES
C0
C0
C0
C0
C0
D0
D0
D0
D0
D0
X3
X3
X3
X3
X3
X3
X3
X3
X3
X3
CRC
CRC
Registers,
X2
X2
X2
X2
X2
X2
X2
X2
X2
X2
X1
X1
X1
X1
X1
X1
X1
X1
X1
X1
33784
Last
Last
X0
X0
X0
X0
X0
X0
X0
X0
X0
X0
17

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