UJA1066TW NXP [NXP Semiconductors], UJA1066TW Datasheet

UJA1066TW

Manufacturer Part Number

UJA1066TW

Description

High-speed CAN fail-safe system basis chip

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.UJA1066TW.pdf (70 pages)

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1. General description

The UJA1066 fail-safe System Basis Chip (SBC) replaces basic discrete components

which are common in every Electronic Control Unit (ECU) with a Controller Area Network

(CAN) interface. The fail-safe SBC supports all networking applications that control

various power and sensor peripherals by using high-speed CAN as the main network

interface. The fail-safe SBC contains the following integrated devices:

In addition to the advantages of integrating these common ECU functions in a single

package, the fail-safe SBC offers an intelligent combination of system-specific functions

such as:

The UJA1066 is designed to be used in combination with a microcontroller that

incorporates a CAN controller. The fail-safe SBC ensures that the microcontroller is

always started up in a defined manner. In failure situations, the fail-safe SBC will maintain

microcontroller functionality for as long as possible to provide a full monitoring and

software-driven fallback operation.

The UJA1066 is designed for 14 V single power supply architectures and for 14 V and

42 V dual power supply architectures.

•

UJA1066

High-speed CAN fail-safe system basis chip

Rev. 03 — 17 March 2010

High-speed CAN transceiver, interoperable and downward compatible with CAN

transceiver TJA1041 and TJA1041A, and compatible with the ISO 11898-2 standard

and the ISO 11898-5 standard (in preparation)

Advanced independent watchdog

Dedicated voltage regulators for microcontroller and CAN transceiver

Serial peripheral interface (full duplex)

Local wake-up input port

Inhibit/limp-home output port

Advanced low-power concept

Safe and controlled system start-up behavior

Advanced fail-safe system behavior that prevents any conceivable deadlock

Detailed status reporting on system and subsystem levels

Product data sheet

Related parts for UJA1066TW

UJA1066TW Summary of contents

Page 1

UJA1066 High-speed CAN fail-safe system basis chip Rev. 03 — 17 March 2010 1. General description The UJA1066 fail-safe System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Controller Area ...

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NXP Semiconductors 2. Features and benefits 2.1 General Contains a full set of CAN ECU functions: CAN transceiver Voltage regulator for the microcontroller (3 5.0 V) Separate voltage regulator for the CAN transceiver (5 V) Enhanced window watchdog ...

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NXP Semiconductors 2.3 Power management Smart operating modes and power management modes Cyclic wake-up capability in Standby and Sleep modes Local wake-up input with cyclic supply feature Remote wake-up capability via the CAN-bus External voltage regulators can easily be incorporated ...

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... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1066TW HTSSOP32 [1] UJA1066TW/5V0 is for the 5 V version; UJA1066TW/3V3 is for the 3.3 V version. 4. Block diagram 31 SENSE 32 BAT42 27 BAT14 29 SYSINH INH/LIMP 7 INTN 18 WAKE WAKE 16 TEST CHIP TEMPERATURE 11 SCK 9 SDI SPI 10 SDO 12 SCS ...

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... SDI SDO SCK SCS TXDC RXDC n.c. TEST UJA1066_2 Product data sheet n. TEST1 4 V1 TEST2 5 RSTN 6 INTN UJA1066TW 9 SDI SDO 10 SCK 11 SCS 12 13 TXDC 14 RXDC n.c. 15 TEST3 16 Pin configuration Pin description Pin Description 1 not connected 2 not connected 3 internally connected; must be left open in the application 4 voltage regulator output for the microcontroller (3 ...

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NXP Semiconductors Table 2. Symbol INH/LIMP WAKE n.c. V2 CANH CANL GND SPLIT i.c. i.c. BAT14 n.c. SYSINH V3 SENSE BAT42 The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via ...

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NXP Semiconductors 6. Functional description 6.1 Introduction The UJA1066 combines all the peripheral functions found around a microcontroller in a typical automotive networking application in a single, dedicated chip. These functions are: • Power supply for the microcontroller • Power ...

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NXP Semiconductors mode change via SPI watchdog trigger Normal mode V1: ON SYSINH: HIGH CAN: all modes available flash entry enabled (111/001/111 mode sequence) watchdog: window OR mode change to Sleep with pending wake-up INH/LIMP: HIGH/LOW/float EN: HIGH/LOW init Normal ...

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NXP Semiconductors 6.2.1 Start-up mode Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a ...

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NXP Semiconductors Entering Normal mode does not activate the CAN transceiver automatically. The CAN Mode Control (CMC) bit must be set to activate the CAN medium if required, allowing local cyclic wake-up scenarios to be implemented without affecting the CAN-bus. ...

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NXP Semiconductors • Cyclic wake-up by the watchdog via an interrupt signal to the microcontroller (the microcontroller is triggered periodically and checked for the correct response) • Cyclic wake-up by the watchdog via a reset signal (a reset is performed ...

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NXP Semiconductors Once in Start-up mode the application software has to write Operating Mode code 011 to the Mode register within t successfully received hardware reset (handshake between the SBC and the microcontroller fed back. The transition from ...

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NXP Semiconductors The following corrupted watchdog accesses result in an immediate system reset: • Illegal watchdog period coding; only ten different codes are valid • Illegal operating mode coding; only six different codes are valid Any microcontroller-driven mode change is ...

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NXP Semiconductors The watchdog window is defined to be between 50 % and 100 % of the nominal programmed watchdog period. Any ‘too early’ or ‘too late’ watchdog access or incorrect Mode register code access will result in an immediate ...

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NXP Semiconductors If the microcontroller supply current rises above I watchdog will be restarted using the watchdog period last used and, if enabled, a watchdog restart interrupt will be generated. In the case of a direct mode change to Standby ...

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NXP Semiconductors The behavior of pin RSTN is illustrated in setting of bit RLC (which defines the reset length). Once an external reset event has been detected, the system controller enters Start-up mode. The watchdog now starts to monitor pin ...

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NXP Semiconductors Pin RSTN is monitored for a continuously clamped LOW condition. If the SBC pulls RSTN HIGH, but it remains LOW for longer than t mode since this indicates an application failure. The SBC also detects if pin RSTN ...

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NXP Semiconductors A dedicated V1 supply comparator (V1 Monitor) monitors V1 for undervoltage events (V O(V1) of the lower V1 undervoltage reset thresholds has been selected (see Regulator V1 is overload protected. The maximum output current available at pin V1 ...

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NXP Semiconductors 6.7 CAN transceiver The integrated high-speed CAN transceiver on the UJA1066 is an advanced ISO 11898-2 and ISO 11898-5 compliant transceiver. In addition to standard high-speed CAN transceiver features, the UJA1066 transceiver provides the following: • Enhanced error ...

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NXP Semiconductors Normal mode OR Flash mode AND CMC = 1 Normal mode OR Flash mode AND CMC = 0 AND CPNC = 0 On-line mode V2: ON/OFF (V2C/V2D) transmitter: OFF RXDC: wake-up (active LOW) SPLIT: ON/OFF (CSC/V2D) CPNC = ...

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NXP Semiconductors 6.7.1.2 On-line mode In On-line mode the CAN-bus pins and pin SPLIT (if enabled) are biased to the normal levels. The CAN transmitter is deactivated and RXDC reflects the CAN wake-up status. A CAN wake-up event is signalled ...

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NXP Semiconductors Fig 9. 6.7.3 Termination control In Active mode, On-line mode and On-line Listen mode, CANH and CANL are terminated to 0.5 × disabled due to an overload condition both pins become floating. 6.7.4 Bus, RXD and ...

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NXP Semiconductors 6.7.4.3 GND shift detection The SBC can detect ground shifts in reference to the CAN-bus. Two different ground shift detection levels can be selected with the GSTHC bit in the Configuration register. The failure can be read out ...

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NXP Semiconductors continuously ON, the WAKE input will be sampled continuously, regardless of the level of bit WSC. The dedicated bits Edge Wake-up Status (EWS) and WAKE Level Status (WLS) in the System Status register reflect the ...

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NXP Semiconductors 6.12 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data ...

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NXP Semiconductors To protect against wrong or illegal SPI instructions, the SBC detects the following SPI failures: • SPI clock count failure (wrong number of clock cycles during one SPI access): only 16 clock periods are allowed during an SCS ...

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NXP Semiconductors 6.12.3 Mode register The Mode register is used to define and re-trigger the watchdog and to select the SBC operating mode. The Mode register also contains the global enable output bit (EN) and the Software Development Mode (SDM) ...

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NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 00 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 01 (as set ...

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NXP Semiconductors Table 6. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 11 (as set in the Special Mode register) [1] The nominal watchdog periods are directly related ...

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NXP Semiconductors Table 7. System Status register bit description Bit Symbol Description RSS[3:0] Reset Source 7 CWS CAN Wake-up Status 6 - reserved 5 EWS Edge Wake-up Status 4 WLS WAKE Level Status 3 TWS Temperature Warning ...

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NXP Semiconductors Table 8. System Diagnosis register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 GSD Ground Shift Diagnosis CANFD [3:0] CAN Failure ...

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NXP Semiconductors Table 8. System Diagnosis register bit description Bit Symbol Description 1 and 0 CANMD [1:0] CAN Mode Diagnosis [1] V2D will be set when V2 is reactivated after a failure. See 6.12.6 Interrupt Enable register and Interrupt Enable ...

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NXP Semiconductors Table 9. Interrupt Enable and Interrupt Enable Feedback register bit description Bit Symbol Description 3 WIE WAKE Interrupt Enable 2 WDRIE Watchdog Restart Interrupt Enable 1 CANIE CAN Interrupt Enable 0 - reserved [1] This bit is cleared ...

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NXP Semiconductors Table 10. Interrupt register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 WTI Watchdog Time-out Interrupt 10 OTI OverTemperature Interrupt 9 GSI Ground Shift ...

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NXP Semiconductors 6.12.8 System Configuration register and System Configuration Feedback register These registers are used to configure the behavior of the SBC. The settings can be read back. Table 11. System Configuration and System Configuration Feedback register bit description Bit ...

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NXP Semiconductors 6.12.9 Physical Layer Control register and Physical Layer Control Feedback register These registers are used to configure the CAN transceiver. The settings can be read back. Table 12. Physical Layer Control and Physical Layer Control Feedback register bit ...

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... V1RTHC [1:0] V1 Reset Threshold Control reserved [1] See Section 6.13.1. [2] Not supported for the UJA1066TW/3V3 version. UJA1066_2 Product data sheet High-speed CAN fail-safe system basis chip Value Function 01 select Special Mode register 0 read the Interrupt Enable Feedback register 1 read the Special Mode Feedback register ...

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NXP Semiconductors 6.12.11 General Purpose registers and General Purpose Feedback registers The UJA1066 contains two 12-bit General Purpose registers (and accompanying General Purpose Feedback registers) without predefined bit definitions. These registers can be used by the microcontroller for advanced system ...

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NXP Semiconductors Table 16. System Status register: status at reset Symbol Name RSS reset source status CWS CAN wake-up status EWS edge wake-up status WLS WAKE level status TWS temperature warning status SDMS software development mode status ENS enable status ...

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NXP Semiconductors Table 20. System Configuration register and System Configuration Feedback register: status at reset Symbol Name GSTHC GND shift level threshold control RLC reset length control V3C V3 control V1CMC V1 current monitor control WEN wake enable WSC wake ...

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NXP Semiconductors Table 22. Special Mode register: status at reset Symbol Name ISDM initialize software development mode ERREM error pin emulation mode WDPRE watchdog prescale factor V1RTHC V1 reset threshold control Table 23. General Purpose register 0 and General Purpose ...

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NXP Semiconductors To remain in Software development mode the SDM bit in the Mode register must be set each time the Mode register is accessed (i.e. watchdog triggering) regardless of how Software development mode was entered. Software development mode can ...

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NXP Semiconductors Table 25. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter V DC voltage on pins DC(n) V1 and V2 V3 and SYSINH INH/LIMP SENSE WAKE ...

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NXP Semiconductors 8. Thermal characteristics Fig 13. Thermal model of the HTSSOP32 package 9. Static characteristics Table 26. Static characteristics − ° ° +150 5 BAT42 ...