UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet - Page 11

• Manufacturer Part Number: UJA1075TW/3V3
• Description: High-speed CAN/LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
UJA1075_2
Product data sheet
Fig 4.
SDO
SCS
SCK
SPI timing protocol
SDI
6.2.2 Register map
floating
X
The first three bits (A2, A1 and A0) of the message header define the register address.
The fourth bit (RO) defines the selected register as read/write or read only.
Table 3.
Address bits 15, 14 and 13
000
001
010
011
X
sampled
01
MSB
MSB
Register map
02
All information provided in this document is subject to legal disclaimers.
14
14
Rev. 02 — 27 May 2010
03
13
13
Write access bit 12 = 0
0 = read/write, 1 = read only
0 = read/write, 1 = read only
0 = read/write, 1 = read only
0 = read/write, 1 = read only
04
12
12
High-speed CAN/LIN core system basis chip
15
01
01
Read/Write access bits 11... 0
WD_and_Status register
Mode_Control register
Int_Control register
Int_Status register
16
LSB
LSB
UJA1075
© NXP B.V. 2010. All rights reserved.
floating
mce634
X
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