ISL6113 INTERSIL [Intersil Corporation], ISL6113 Datasheet - Page 11

• Manufacturer Part Number: ISL6113
• Description: Dual Slot PCI-E Hot Plug Controllers
• Manufacturer: INTERSIL [Intersil Corporation]

the ISL6113, ISL6114 respectively, C
capacitance, and C
including C
capacitance connected from the GATE output pin to the
GATE reference, GND or source.
An estimate for the output slew rate of 3.3V outputs and 12V
outputs where there is little or no external 12VGATE output
capacitors, can be taken from Equation 2:
where I
capacitance. Note: As a consequence, the CR duration,
t
fully charge the output load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate
Control)
The 3.3V outputs act as source followers. In this mode of
operation, V
associated output reaches 3.3V. The voltage on the gate of
the MOSFET will then continue to rise until it reaches 12V,
which ensures minimum r
the MOSFET is optionally configured as a Miller integrator to
adjust the V
connected between the MOSFET’s gate and drain. In this
configuration, the feedback action from drain to gate of the
MOSFET causes the voltage at the drain of the MOSFET to
slew in a linear fashion at a rate estimated by Equation 3:
Tables 1 and 2 approximate the output slew-rate for various
values of C
capacitance (external C
C
12V rail).
VOUTdv/dt
ISL6113
*Values in this range will be affected by the internal parasitic
capacitances of the MOSFETs used and should be verified
empirically.
FILTER
ISL6114
GS
TABLE 1. ISL6113 3.3V AND 12V OUTPUT SLEW-RATE
CGATE or C
of the external MOSFET for the 3.3V rail; C
LIM
0.022µF*
must be programmed to exceed the time it takes to
0.047µF
0.01µF*
0.1µF
VOUTdv/dt
VOUTdv/dt
ISS
GATE
= 50mV/R
OUT
SOURCE
=
SELECTION FOR GATE CAPACITANCE
DOMINATED START-UP
------------------- -
C
of the external MOSFET and any external
I
LOAD
GD
LIM
ramp time by having a C
when start-up is dominated by GATE
GATE
SENSE
= [V
=
=
| IGATE | = 25µA
GATE
25μA
-------------- -
------------
C
5μA
C
is the total GATE capacitance
DS(ON)
GD
GATE
GD
11
and C
from GATE pin to ground plus
– V
. For the 12V outputs, when
TH(ON)
LOAD
dv/dt (LOAD)
LOAD
0.532 V/ms
1.136V/ms
0.250V/ms
2.5V/ms
is the load
GD
] until the
is the load
, which is
GD
for the
ISL6113, ISL6114
(EQ. 2)
(EQ. 3)
During turn-on, the ISL6113 invokes the current regulation
(CR) feature to limit inrush current whereas the ISL6114
disables the CR feature during turn-on thus allowing a
shorter programmed t
or Way Overcurrent (WOC) condition such as a short at this
time.
Note that all of these performance estimates and guidelines
are useful only for first order time and loading expectations,
as they do not look at other significant loading factors.
Figures 3 through 11 realistically illustrate the discussed
turn-on performance topic with the noted loading and
compensation conditions. Notice the degree of control over
the in-rush current and the GATE ramp rate as the C
C
turn on characteristics.
In some scope shots although the C
in the absence of excessive displayed loading current the
C
is not displayed.
All scope shots were taken from the ISL6113EVAL1Z or
ISL6114EVAL1Z platform with any component changes are
noted.
*
capacitances of the MOSFETs used and should be verified
empirically.
Values in this range will be affected by the internal parasitic
GS
FILTER
TABLE 2. ISL6114 3.3V AND 12V OUTPUT SLEW-RATE
FIGURE 3. ISL6113 12VMAIN START-UP R
values are changed providing for highly customized
CGATE or C
is responding to the other MAIN supply current that
0.022µF*
0.047µF
0.01µF*
0.1µF
SELECTION FOR GATE CAPACITANCE
DOMINATED START-UP
C
LOAD
GD
= 470µF
FILTER
| IGATE | = 5µA
. Both ICs monitor for a severe
FILTER
dv/dt (LOAD)
0.106 V/ms
0.050V/ms
0.23V/ms
0.5V/ms
C
C
GD
GS
LOAD
shows a ramping
= 6.8nF
= 22nF
September 25, 2007
= 10Ω,
12 IOUT
C
12V
12V
FILTER
GD
GATE
OUT
FN6457.0
and