DP8473N NSC [National Semiconductor], DP8473N Datasheet - Page 5

• Manufacturer Part Number: DP8473N
• Description: DP8473 Floppy Disk Controller PLUS-2
• Manufacturer: NSC [National Semiconductor]

Typical Application
Recommended Plastic Chip Carrier Socket
Functional Description
This section describes the basic architectural features of
the DP8473 and many of the enhancements provided Re-
fer to Figure 1
765A COMPATIBLE MICRO-ENGINE
The core of the DP8473 is a
coded engine This engine consists of a sequencer pro-
gram ROM and disk misc registers This core is clocked by
either a 4 MHz 4 8 MHz or 8 MHz clock selected in the Data
Rate Register Upon this core is added all the glue logic
used to implement a PC-XT or AT or PS 2 floppy controller
as well as the data separator and write precompensation
logic
The controller consists of a microcoded engine that controls
the entire operation of the chip including coordination of
data transfer with the CPU controlling the drive controls
and actually performing the algorithms associated with
reading and writing data to from the disk This includes the
read algorithm for the data separator
Like the PD765A this controller takes commands and re-
turns data and status through the Data Register in a byte
serial fashion Handshake for command status I O is pro-
vided via the Main Status Register All of the
commands are supported as are many other enhanced
commands
AMP P N 821551-1 or equivalent
PD765A compatible micro-
FIGURE 2 DP8473 Typical Application
PD765A
5
ure 3
DATA SEPARATOR
The internal data separator consists of an analog PLL and
its associated circuitry The PLL synchronizes the raw data
signal read from the disk drive The synchronized signal is
used to separate the encoded clock and data pulses The
data pulses are de-serialized into bytes and then sent to the
The main PLL consists of four main components a phase
comparator a filter a voltage controlled oscillator (VCO)
and a programmable divider The phase comparator detects
the difference between the phase of the divider’s output and
the phase of the raw data being read from the disk This
phase difference is converted to a current which either
charges or discharges one of the three external filters The
resulting voltage on the filter changes the frequency of the
VCO and the divider output to reduce the phase difference
between the input data and the divider’s output The PLL is
‘‘locked’’ when the frequency of the divider is exactly the
same as the average frequency of the data read from the
disk A block diagram of the data separator is shown in Fig-
P by the controller
TL F 9384 – 4