DP8473N NSC [National Semiconductor], DP8473N Datasheet - Page 6

• Manufacturer Part Number: DP8473N
• Description: DP8473 Floppy Disk Controller PLUS-2
• Manufacturer: NSC [National Semiconductor]

Functional Description
Note For all filter configurations 250kb s and 300 kb s share the same filter
To ensure optimal performance the data separator incorpo-
rates several additional circuits The quarter period delay
line is used to determine the center of each bit cell A sec-
ondary PLL is used to automatically calibrate the quarter
period delay line The secondary PLL also calibrates the
center frequency of the VCO
To eliminate the logic associated with controlling multiple
data rates the DP8473 supports the connection of three
filters to the chip via the FGND250 and FGND500 pins (fil-
ter ground switches) The controller chooses which filter
components to use based on the value loaded in the Data
Rate Register If 500 k(MFM) is being used then the
FGND500 is enabled (FGND250 is disabled) If 250 k(MFM)
or 300 k(MFM) is being used the FGND250 pin is enabled
and FGND500 is disabled For 1 Mb s (MFM) both FGND
pins are disabled
Note for FM encoding Sometimes after a reset the DP8473 will consist-
ently return an error in the Result Phase after an FM read command If this
occurs simply reset the DP8473 and retry the operation This may have to
be done more than once as many as five times Resetting and repeating will
prevent soft errors being reported prematurely This technique is used by
MS-DOS
a) Single Data Rate
FIGURE 4 Typical Configuration for Loop Filters for the DP8473 Showing Component Labels
TL F 9384– 6
FIGURE 3 Block Diagram of DP8473’s Data Separator
(Continued)
b) 250 500 kb s Filter
6
Figure 4 shows several possible filter configurations For a
filter to cover all data rates ( Figure 4c ) the DP8473 has a 1
Mb s filter always connected and other capacitor filter com-
ponents for the other data rates are switched in parallel to
this filter The actual loop filter for 500 kb s is the parallel
combination of the two capacitors C
to the FGND500 pin and to ground The 250 300 kb s filter
is the parallel combination of the capacitors C
attached to the FGND250 and ground If 1 Mb s need not
be supported then the filter configuration of Figure 4b can
be used This configuration allows more optimal perform-
ance for both 500k and 250 300 kb s Figure 4a is a simple
filter configuration primarily for a single data rate (or multiple
data rates with a performance compromise) Table II shows
some typical filter values Other filter configurations and val-
ues are possible these result in good general performance
While the controller and data separator support both FM
and MFM encoding the filter switch circuitry only supports
TL F 9384 – 7
c) 250 500 kb s and 1 Mb s
2C
and C
2B
2C
TL F 9384– 5
TL F 9384– 8
and C
attached
2A