AN983 ETC [List of Unclassifed Manufacturers], AN983 Datasheet - Page 16

no-image

AN983

Manufacturer Part Number
AN983
Description
PCI/miniPCI-to-Ethernet LAN Controller
Manufacturer
ETC [List of Unclassifed Manufacturers]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AN983B
Manufacturer:
ADMTEK
Quantity:
672
Part Number:
AN983B
Manufacturer:
ADMTEK
Quantity:
1 000
Part Number:
AN983B
Manufacturer:
INFIN
Quantity:
1 000
Part Number:
AN983B
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Company:
Part Number:
AN983B
Quantity:
98
Part Number:
AN983B-BG-T-V8
Manufacturer:
Infineon Technologies
Quantity:
10 000
Part Number:
AN983BLX-BG-T-V1
Manufacturer:
Infineon Technologies
Quantity:
10 000
Part Number:
AN983BX-BG-R-V1
Manufacturer:
Infineon Technologies
Quantity:
10 000
Part Number:
AN983BX-BG-T-V1
Manufacturer:
INFINEON/英飞凌
Quantity:
20 000
Part Number:
AN983BX-BG-T-V8
Manufacturer:
LANTIQ
Quantity:
800
Part Number:
AN983X-AH-T-21
Manufacturer:
CY
Quantity:
1 045
43
57
69
83
44
59
60
61
63
64
65
66
68
92
98~101,
106,108
~110,
112,
113,
126,
127,
128,
1~3, 105
116~
120,
121~
123,
124
125
114
Rev. 1.8
BOOTROM/EEPROM INTERFACE
C-BEB3
C-BEB2
C-BEB1
C-BEB0
IDSEL
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PAR
Clk-run
BrA0 ~16
BrD0~4
BrD5/EDO
BrD6/EDI
BrD7/ECK
EECS
BrCS#
BrOE#
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
O/D
I/O
I/O
O/D
I/O
IO
IO/O
IO/I
IO/I
O
O
O
Bus command and byte enable
Initialization Device Select. This signal is asserted when host issues the
configuration cycles to the AN983B.
Begin and duration of bus access, driven by master device
Master device is ready to data transaction
Slave device is ready to data transaction
Device select, target is driving to indicate the address is decoded
Target device request the master device to stop the current transaction
Data parity error is detected, driven by the agent receiving data
Address parity error
Parity, even parity (AD [31:0] + C/BE [3:0]), master drives par for address
and write data phase, target drives par for read data phase
Clock Run for PCI system. In the normal operation situation, Host should
assert this signal to indicate AN983B about the normal situation. On the
other hand, when Host will deassert this signal when the clock is going down
to a non-operating frequency. When AN983B recognizes the deasserted
status of clk-run, then it will assert clk-run to request host to maintain the
normal clock operation. When clk-run function is disabled then the AN983B
will set clk-run in tri-state.
ROM data bus
Provides up to 128kB EPROM or Flash-ROM application space.
BootROM data bus bit (0~7)
Inputs/Output data for AN983B; EDO: Data Output of serial EEPROM
Inputs/Output data for AN983B; EDI: Data Input of serial EEPROM
Inputs/Output data for AN983B; ECK: Clock input of serial EEPROM, the
AN983B outputs clock signal to EEPROM
Chip Select of serial EEPROM
BootROM Chip Select
BootROM Read Enable for flash ROM application
AN983B
www.admtek.com.tw
ADMtek Inc.
PCI/miPCI Fast Ethernet Controller with integrated PHY
16

Related parts for AN983