SAB-C167SR-LM SIEMENS [Siemens Semiconductor Group], SAB-C167SR-LM Datasheet - Page 28

• Manufacturer Part Number: SAB-C167SR-LM
• Description: 16-Bit CMOS Single-Chip Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

C167SR
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to
distinguish address from data bytes has been included (8-bit data + wake up bit mode).
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock
which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length
synchronously to a shift clock which can be generated by the SSC (master mode) or by an external
master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0
always shifts the LSB first.
A loop back option is available for testing purposes.
A number of optional hardware error detection capabilities has been included to increase the
reliability of data transfers. A parity bit can automatically be generated on transmission or be
checked on reception. Framing error detection allows to recognize data frames with missing stop
bits. An overrun error will be generated, if the last character received has not been read out of the
receive buffer register at the time the reception of a new character is complete.
Parallel Ports
The C167SR provides up to 111 I/O lines which are organized into eight input/output ports and one
input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise)
programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports
which are switched to high impedance state when configured as inputs. The output drivers of five
I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation via control
registers. During the internal reset, all port pins are configured as inputs.
The input threshold of Port 2, Port 3, Port 7 and Port 8 is selectable (TTL or CMOS like), where the
special CMOS like input threshold reduces noise sensitivity due to the input hysteresis. The input
threshold may be selected individually for each byte of the respective ports.
All port lines have programmable alternate input or output functions associated with them.
PORT0 and PORT1 may be used as address and data lines when accessing external memory,
while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where
segmentation is enabled to access more than 64 KBytes of memory.
Port 2, Port 8 and Port 7 are associated with the capture inputs or compare outputs of the CAPCOM
units and/or with the outputs of the PWM module.
Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals.
Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE
and the system clock output (CLKOUT).
Port 5 is used for the analog input channels to the A/D converter or timer control signals.
All port lines that are not used for these alternate functions may be used as general purpose IO
lines.
Semiconductor Group
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