AT89C51RB2-RLTCM ATMEL [ATMEL Corporation], AT89C51RB2-RLTCM Datasheet - Page 47

• Manufacturer Part Number: AT89C51RB2-RLTCM
• Description: 8-bit Microcontroller with 16K/ 32K Bytes Flash
• Manufacturer: ATMEL [ATMEL Corporation]

4180B–8051–04/03
Table 33. SCON Register
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
FE/SM0
Number
7
Bit
7
6
5
4
3
2
1
0
SM1
Mnemonic
6
REN
SM0
SM1
SM2
RB8
TB8
Bit
FE
TI
RI
SM2
5
Description
Framing Error bit (SMOD0 = 1)
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit.
Serial Port Mode bit 0
see SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit.
Serial Port Mode bit 1
SM0
0
0
1
1
Serial Port Mode 2 bit/Multiprocessor Communication Enable bit
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in modes 2 and 3,
and eventually mode 1.This bit should be cleared in mode 0.
Reception Enable bit
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8/Ninth bit to Transmit in Modes 2 and 3
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8/Ninth bit received in Modes 2 and 3
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not
used.
Transmit Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning
of the stop bit in the other modes.
Receive Interrupt flag
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 17.
and Figure 18 in the other modes.
SM1
0
1
0
1
REN
4
Mode Description
0
1
2
3
Shift Register
8-bit UART
9-bit UART
9-bit UART
TB8
3
AT89C51RB2/RC2
Baud Rate
F
Variable
F
Variable
RB8
CPU PERIPH
CPU PERIPH
2
/6
/32 or /16
1
TI
RI
0
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