SAF-C515-L24M SIEMENS [Siemens Semiconductor Group], SAF-C515-L24M Datasheet - Page 39

• Manufacturer Part Number: SAF-C515-L24M
• Description: 8-Bit CMOS Microcontroller
• Manufacturer: SIEMENS [Siemens Semiconductor Group]

Power Saving Modes
The C515 provides two basic power saving modes, the idle mode and the power down mode.
Additionally, a slow down mode is available. This power saving mode reduces the internal clock
rate in normal operating mode and it can be also used for further power reduction in idle mode.
Table 8 gives a general overview of the entry and exit procedures of the power saving modes.
Table 8
Power Saving Modes Overview
Mode
Idle mode
Power Down Mode
Slow Down Mode
In the power down mode of operation,
be ensured, however, that
is restored to its normal operating level, before the power down mode is terminated.
Semiconductor Group
– Idle mode
– Power down mode
– Slow-down mode
The CPU is gated off from the oscillator. All peripherals are still provided with the clock and
are able to work. Idle mode is entered by software and can be left by an interrupt or reset.
The operation of the C515 is completely stopped and the oscillator is turned off. This mode is
used to save the contents of the internal RAM with a very low standby current. Power down
mode is entered by software and can be left by reset or by a short low pulse at pin P3.2/INT0.
The controller keeps up the full operating functionality, but its normal clock frequency is
internally divided by 8. This slows down all parts of the controller, the CPU and all peripherals,
to 1/8 th of their normal operating frequency. Slowing down the frequency significantly
reduces power consumption.
Entering
2-Instruction
Example
ORL PCON, #01H
ORL PCON, #20H
ORL PCON, #02H
ORL PCON, #40H
In normal mode :
ORL PCON,#10H
With idle mode :
ORL PCON,#01H
ORL PCON, #30H
V
CC
is not reduced before the power down mode is invoked, and that
V
CC
can be reduced to minimize power consumption. It must
Leaving by
Occurrence of an
interrupt from a
peripheral unit
Hardware Reset
Hardware Reset
ANL PCON,#0EFH
or
Hardware Reset
Occurrence of an
interrupt from a
peripheral unit
Hardware reset
39
Remarks
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with
clock
Oscillator is stopped;
contents of on-chip RAM and
SFR’s are maintained;
Internal clock rate is reduced
to 1/8 of its nominal frequency
CPU clock is stopped;
CPU maintains their data;
peripheral units are active (if
enabled) and provided with 1/8
of its nominal frequency
1997-08-01
C515
V
CC