SAF-XC164GM-8F20F INFINEON [Infineon Technologies AG], SAF-XC164GM-8F20F Datasheet - Page 61

• Manufacturer Part Number: SAF-XC164GM-8F20F
• Description: 16-Bit Single-Chip Microcontroller with C166SV2 Core
• Manufacturer: INFINEON [Infineon Technologies AG]

This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
the number of VCO cycles can be represented as K
consecutive
For a period of N
D
So, for a period of 3 TCMs @ 20 MHz and K = 12: D
This formula is applicable for K
used. This steady value can be approximated by: D
Figure 4-6
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
Data Sheet
N
[ns] = (1.5 + 6.32
selecting the maximum possible output prescaler factor K.
Acc. jitter
±8
±7
±6
±5
±4
±3
±2
±1
ns
f
0
MC
Approximated Accumulated PLL Jitter
0
cycles (TCM).
1
10 MHz
40 MHz
D
TCM the accumulated PLL jitter is defined by the deviation D
N
N /
K = 15
5
20 MHz
f
MC
K = 12
);
f
N < 95. For longer periods the K N = 95 value can be
MC
K = 10
10
in [MHz], N = number of consecutive TCMs.
K = 8
59
K = 6 K = 5
15
3
Nmax
= (1.5 + 6.32 3 / 20) = 2.448 ns.
[ns] = (1.5 + 600 / (K
N, where N is the number of
20
Electrical Parameters
25
MCD05566
f
MC
Derivatives
V1.0, 2005-11
XC164GM
. Therefore,
N
N
f
MC
:
)).