ISL8033A INTERSIL [Intersil Corporation], ISL8033A Datasheet - Page 14

• Manufacturer Part Number: ISL8033A
• Description: Dual 3A Low Quiescent Current High Efficiency Synchronous Buck Regulator
• Manufacturer: INTERSIL [Intersil Corporation]

Typical Operating Performance ISL8033A
Unless otherwise noted, operating conditions are: T
V
Theory of Operation
The ISL8033 is a dual 3A step-down switching regulator
optimized for battery-powered or mobile applications.
The regulator operates at 1MHz fixed switching
frequency under heavy load condition. The ISL8033A
operates at 2.5MHz to allow small external inductor and
capacitors to be used for minimal printed-circuit board
(PCB) area. The two channels are 180° out-of-phase
operation. The supply current is typically only 8µA when
the regulator is shutdown.
PWM Control Scheme
Pulling the SYNC pin HI (>1.5V) forces the converter into
PWM mode in the next switching cycle regardless of
output current. Each of the channels of the ISL8033,
ISL8033A employ the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting, as shown
in the “Theory of Operation” on page 14. The current
loop consists of the oscillator, the PWM comparator
COMP, current sensing circuit, and the slope
compensation for the current loop stability. The current
sensing circuit consists of the resistance of the P-channel
MOSFET when it is turned on and the current sense
amplifier CSA1. The gain for the current sensing circuit is
typically 0.20V/A. The control reference for the current
loops comes from the error amplifier EAMP of the voltage
loop.
The PWM operation is initialized by the clock from the
oscillator. The P-channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the
MOSFET starts to ramp-up. When the sum of the
current amplifier CSA1 (or CSA2 on Channel 2) and the
compensation slope (0.46V/µs) reaches the control
reference of the current loop, the PWM comparator
COMP sends a signal to the PWM logic to turn off the
OUT1
= 1.2V, V
FIGURE 37. LOAD TRANSIENT CHANNEL 1
OUT2
= 1.8V, I
V
OUT1
14
OUT1
IL1 2A/DIV
RIPPLE 50mV/DIV
= I
OUT2
= 0A to 3A. (Continued)
A
ISL8033, ISL8033A
= +25°C, V
IN
= 5V, EN = V
P-MOSFET and to turn on the N-channel MOSFET. The
N-MOSFET stays on until the end of the PWM cycle.
Figure 39 shows the typical operating waveforms during
the PWM operation. The dotted lines illustrate the sum
of the compensation ramp and the current-sense
amplifier CSA_ output.
The output voltage is regulated by controlling the
reference voltage to the current loop. The bandgap
circuit outputs a 0.8V reference voltage to the voltage
control loop. The feedback signal comes from the VFB
pin. The soft-start block only affects the operation during
the start-up and will be discussed separately. The error
amplifier is a transconductance amplifier that converts
the voltage error signal to a current output. The voltage
loop is internally compensated with the 27pF and 390kΩ
RC network. The maximum EAMP voltage output is
precisely clamped to the bandgap voltage (1.172V).
Cycle
V
V
Duty
V
EAMP
CSA1
OUT
I
L
FIGURE 39. PWM OPERATION WAVEFORMS
FIGURE 38. LOAD TRANSIENT CHANNEL 2
IN
, L1 = 0.68µH, L2 = 1µH, C1 = C2 = C4 = 2x22µF,
V
OUT2
IL2 2A/DIV
RIPPLE 50mV/DIV
October 21, 2010
FN6854.1