ISL89160 INTERSIL [Intersil Corporation], ISL89160 Datasheet - Page 9

• Manufacturer Part Number: ISL89160
• Description: High Speed, Dual Channel, 6A, 4.5 to 16VOUT, Power MOSFET Driver
• Manufacturer: INTERSIL [Intersil Corporation]

In Figure 14, R
input signal. For the falling edge of the input signal, the
diode shorts out the resistor resulting in a minimal falling
edge delay. If the diode polarity is reversed, the falling
edge is delayed and the rising delay is minimal.
The 37% and 63% thresholds were chosen to simplify
the calculations for the desired time delays. When using
an RC circuit to generate a time delay, the delay is simply
T (secs) = R (ohms) x C (farads). Please note that this
equation only applies if the input logic voltage amplitude
is 3.3V. If the logic high amplitude is higher than 3.3V,
the equations in EQ 1 can be used for more precise delay
calculations.
In this example, the high input logic voltage is 5V, the
positive threshold is 63% of 3.3V and the low level input
logic is 0.1V. Note the rising edge propagation delay
of the driver must be added to this value.
The minimum recommended value of C is 100pF. The
parasitic capacitance of the PCB and any attached scope
probes will introduce significant delay errors if smaller
values are used. Larger values of C will further minimize
errors.
Acceptable values of R are primarily effected by the
source resistance of the logic inputs. Generally, 100Ω
resistors or larger are usable. A practical maximum
value, limited by contamination on the PCB, is 1MΩ.
Power Dissipation of the Driver
The power dissipation of the ISL89160, ISL89161,
ISL89162 is dominated by the losses associated with the
gate charge of the driven bridge FETs and the switching
frequency. The internal bias current also contributes to
the total dissipation but is usually not significant as
compared to the gate charge losses.
t del
V H
V
V
R
C
t del
THRESH
L
del
del
=
=
=
=
=
=
0.1V
5V
51.731ns
–
100Ω
1nF
R del C del
=
63%
×
×
del
LN
3.3V
and C
⎛
⎜
⎝
V L V THRESH
--------------------------------------------
High level of the logic signal into the RC
Positive going threshold
Low level of the logic signal into the RC
Timing values
Nominal delay time
–
V
H
del
–
V
L
9
delay the rising edge of the
+
1
⎞
⎟
⎠
ISL89160, ISL89161, ISL89162
(EQ. 1)
Figure 15 illustrates how the gate charge varies with
the gate voltage in a typical power MOSFET. In this
example, the total gate charge for V
when V
source to turn-on the MOSFET and must sink to
turn-off the MOSFET.
Equation 2 shows calculating the power dissipation of
the driver:
P
where:
freq = Switching frequency,
V
Q
I
(see Figure 7)
r
R
Note that the gate power dissipation is proportionally
shared with the external gate resistor and the output
r
overlook the power dissipated by this resistor.
DD
DS(ON)
DS(ON)
FIGURE 15. MOSFET GATE CHARGE vs GATE VOLTAGE
D
GS
gate
c
= Gate charge for V
=
(freq) = Bias current at the switching frequency
= V
2 Q
= External gate resistance (if any).
12
10
•
DS
8
6
4
2
0
. When sizing an external gate resistor, do not
DD
= ON-resistance of the driver
0
c
•
= 40V. This is the charge that a driver must
freq V
bias of the ISL89160, ISL89161, ISL89162
2
•
4
GS
6
•
Q
-------------------------------------------- -
R
g,
V
8
GS
gate
DS
GATE CHARGE (nC)
10 12 14 16 18 20 22 24
R
= 40V
+
gate
r
V
DS ON
DS
(
= 64V
)
gs
+
I
DD
= 10V is 21.5nC
(
freq
November 2, 2010
) V
•
(EQ. 2)
DD
FN7719.0