AD8197B-EVALZ AD [Analog Devices], AD8197B-EVALZ Datasheet - Page 15

• Manufacturer Part Number: AD8197B-EVALZ
• Description: 4:1 HDMI/DVI Switch with Equalization
• Manufacturer: AD [Analog Devices]

SERIAL CONTROL INTERFACE
RESET
On initial power-up, or at any point in operation, the AD8197B
register set can be restored to the status of the parallel control
interface pins and some preprogrammed default values by
pulling the RESET pin to low, in accordance with the specifica-
tions in Table 1. During normal operation, however, the RESET
pin must be pulled up to 3.3 V. Following a reset, the prepro-
grammed default values of the AD8197B register set correspond
to the state of the parallel interface configuration registers and
defaults, as listed in Table 18. The AD8197B can be controlled
through the parallel control interface until the first serial
control event occurs. As soon as any serial control event occurs,
the serial programming values, corresponding to the state of the
serial interface configuration registers (Table 5), override any
prior parallel programming values, and the parallel control
interface is disabled until the part is subsequently reset.
Note that the input termination resistor switch control is only
via I
these switches cannot operate in parallel control mode.
WRITE PROCEDURE
To write data to the AD8197B register set, an I
as a microcontroller) needs to send the appropriate control
signals to the AD8197B slave device. The signals are controlled
by the I
the procedure, see Figure 29. The steps for a write procedure are
as follows:
1.
2.
2
Send a start condition (while holding the I2C_SCL line
high, pull the I2C_SDA line low).
Send the AD8197B part address (seven bits). The upper
four bits of the AD8197B part address are the static value
[1001] and the three LSBs are set by Input Pin I2C_ADDR2,
Input Pin I2C_ADDR1, and Input Pin I2C_ADDR0 (LSB).
This transfer should be MSB first.
GENERAL CASE
C control. Therefore, any system that requires control of
2
C master, unless otherwise specified. For a diagram of
EXAMPLE
I2C_SDA
I2C_SDA
I2C_SCL
*THE SWITCHING/UPDATE DELAY BEGINS AT THE FALLING EDGE OF THE
LAST DATA BIT; FOR EXAMPLE, THE FALLING EDGE JUST BEFORE STEP 8.
START
1
2
FIXED PART
ADDR
ADDR
2
C master (such
R/W
3
ACK
Figure 29. I
4
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5
2
REGISTER ADDR
C Write Diagram
3.
4.
5.
6.
7.
8.
9.
Send the write indicator bit (0).
Wait for the AD8197B to acknowledge the request.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
Wait for the AD8197B to acknowledge the request.
Send the data (eight bits) to be written to the register
whose address was set in Step 5. This transfer should be
MSB first.
Wait for the AD8197B to acknowledge the request.
Perform one of the following:
9a. Send a stop condition (while holding the I2C_SCL
9b. Send a repeated start condition (while holding the
9c. Send a repeated start condition (while holding the
9d. Send a repeated start condition (while holding the
line high, pull the I2C_SDA line high) and release
control of the bus to end the transaction (shown in
Figure 29).
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 in this procedure to perform
another write.
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 2 of the read procedure (in the
Read Procedure section) to perform a read from
another address.
I2C_SCL line high, pull the I2C_SDA line low) and
continue with Step 8 of the read procedure (in the
Read Procedure section) to perform a read from the
same address set in Step 5.
ACK
6
7
DATA
*
ACK
8
AD8197B
STOP
9