STA015B STMICROELECTRONICS [STMicroelectronics], STA015B Datasheet
STA015B
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STA015B Summary of contents
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... D/A converter, by the PCM Out- put Interface. This interface is software program- mable to adapt the STA015 digital output to the most common DACs architectures used on the market. The functional STA015 chip partitioning is de- scribed in Fig.1 and Fig.2. PRODUCT PREVIEW STA015T (TQFP44) STA015B (LFBGA 64) 1/44 ...
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... STA015-STA015B-STA015T Figure 1a. BLOCK DIAGRAM for TQFP44 and LFBGA64 package TQFP44 34 SDI SERIAL 36 SCKR INPUT INTERFACE 38 BIT_EN 27 BUFFER DATA-REQ 256 SCK_ADC ADC 26 CRCK_ADC INPUT INTERFACE 24 SDI_ADC 25 15 RESET XTI Figure 1b. BLOCK DIAGRAM for SO28 package SO28 5 SDI SERIAL 6 SCKR INPUT INTERFACE ...
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... C8 = VDD_4 F2 = SCKT D7 = TESTEN H1 = LRCKT A7 = SDI_ADC H3 = OCLK B6 = RESET F3 = VSS_2 A5 = LRCK_ADC E4 = VDD_2 C5 = OUT_CLK/DATA_REQ G4 = VSS_3 B5 = VDD_1 G5 = VDD_3 B4 = VSS_1 F5 = PVDD A4 = SDA G6 = PVSS B3 = SCL LFBGA64 STA015-STA015B-STA015T C2 = GPIO_STROBE C3 = IODATA [ IODATA [ IODATA [ IODATA [ GPSO_REQ F8 = IODATA [ IODATA [ IODATA [ IODATA [ GPSO_SCKR A2 = GPSO_DATA 3/44 ...
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... STA015-STA015B-STA015T 1. OVERVIEW 1.1 - MP3 decoder engine The MP3 decoder engine is able to decode any Layer III compliant bitstream: MPEG1, MPEG2 and MPEG2.5 streams are supported. Besides audio data decoding the MP3 engine also per- forms ANCILLARY data extraction: these data can be retrieved via I2C bus by the application microcontroller in order to implement specific functions ...
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... F1 IODATA[ GPIO_STROBE 4 G3 GPSO_REQ 28 C6 GPSO_SCKR 33 A2 GPSO_DATA Note: In functional mode TESTEN must be connected to VDD. STA015-STA015B-STA015T Type Function Supply Voltage Ground 2 I Serial Data + CMOS Input Pad Buffer Acknowledge CMOS 4mA Output Drive Serial Clock CMOS Input Pad Buffer ...
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... STA015-STA015B-STA015T 1. ELECTRICAL CHARACTERISTICS: V specified DC OPERATING CONDITIONS Symbol Parameter V Power Supply Voltage DD T Operating Junction Temperature j GENERAL INTERFACE ELECTRICAL CHARACTERISTICS Symbol Parameter I Low Level Input Current IL Without pull-up device I High Level Input Current IH Without pull-up device V Electrostatic Protection esd Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin ...
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... The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example TTL min high level = 2.0V while XTI min high level = 2.2V) STA015-STA015B-STA015T SDA 3 28 SCL ...
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... STA015-STA015B-STA015T Figure 5. PLL and Clocks Generation System XTI N FRAC Update FRAC 2.4 - PCM Output Interface The decoded audio data are output in serial PCM format. The interface consists of the following sig- nals: SDO PCM Serial Data Output SCKT PCM Serial Clock Output LRCLK ...
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... To compensate the difference between the nomi- nal and the real sampling rates, the STA015 em- bedded software controls the fractional PLL op- eration. Portable or Mobile applications need STA015-STA015B-STA015T normally to operate in Broadcast Mode. In both modes the MPEG Synchronisation is automatic and transparent to the user. 2.6 - STA015 Decoding States There are three different decoder states: Idle, Init, and Decode ...
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... STA015-STA015B-STA015T Figure 8. MPEG Decoder Interfaces. DATA_REQ SDI DATA SCKR SOURCE BIT_EN D98AU912 Figure 9. Serial Input Interface Clocks SDI SCKR SCKR BIT_EN DATA VALID 2.2 - Serial Input Interface STA015 receives the input data (MSB first) thought the Serial Input Interface (Fig.5 serial communication interface connected to the SDI (Serial Data Input) and SCKR (Receiver Se- rial Clock) ...
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... Figure. 11 LRCK_ADC SDI_ADC ADC I/F SCK_ADC SDI SCKR SERIAL RECEIVER DATA_REQ STA015-STA015B-STA015T GPSO_SCKR GPSO_DATA STA015 MCU GPSO_REQ D00AU1145 ADPCM to provide an interrupt; the use of the other bits is still to be defined. The related con- figuration register is GPIO_CONF. See the follow- ing summary for related pin usage: ...
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... STA015-STA015B-STA015T The following 4 figures (fig. 12, 13, 14, 15) show the available connection diagrams as for as ADPCM encoding function. As shown in the fig- ures some configuration is not available in SO28 package. Figure 13. Input from ADC, Output from I2C + IRQ DATA_REQ LRCKT SCKT MCU SDI_ADC STA015 ...
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... DEV-ADDR SUB-ADDR RANDOM READ START RW STA015-STA015B-STA015T The 7 most significant bits are the device address identifier, corresponding to the I For the STA015 these are fixed as 1000011. The 8th bit (LSB) is the read or write operation RW, this bit is set read mode and 0 for write mode. After a START condition the STA015 ...
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... STA015-STA015B-STA015T 3.4 - READ OPERATION (see Fig. 17) 3.4.1 - Current byte address read The STA015 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. For the current byte address read mode, follow- ing a START condition the master sends the de- vice address with the RW bit set to 1. ...
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... ADC_ WLEN $C1 193 ADC_ WPOS $C2 194 ADPCM_SKIP_FRAME Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use. STA015-STA015B-STA015T DESCRIPTION RESET 0xFF 0x5B 0x0F R/W R/W (8) 0x00 R/W (2) 0x00 R/W (1) ...
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... STA015-STA015B-STA015T 4.1 - STA015 REGISTERS DESCRIPTION 2 The STA015 device includes 256 I this document, only the user-oriented registers are described. The undocumented registers are reserved. These registers must never be ac- cessed (in Read or in Write mode). The Read- Only registers must never be written. The following table describes the meaning of the ...
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... If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR and sampled on the falling edge. ERROR_CODE Address: 0x0F (15) Type: RO Software Reset: 0x00 Hardware Reset: 0x00 STA015-STA015B-STA015T MSB EC5 X = don’t care ERROR_CODE register contains the last error occourred if any ...
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... STA015-STA015B-STA015T MUTE Address: 0x14 (20) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB don’t care normal operation mute The MUTE command is handled according to the state of the decoder, as described in section 2.5. MUTE sets the clock running. DATA_REQ_ENABLE ...
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... H20 H19 H18 x = don’t care HEAD_M[15:8] MSB H15 H14 H13 H12 H1‘1 H10 STA015-STA015B-STA015T HEAD_L[7:0] MSB Address: 0x43, 0x44, 0x45 (67, 68, 69) LSB b1 b0 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis Head[2] original/copy ...
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... STA015-STA015B-STA015T Bitrate_index indicates the bitrate (Kbit/sec) depending on the MPEG ID. bitrate index ’0000’ free ’0001’ 32 ’0010’ 40 ’0011’ 48 ’0100’ 56 ’0101’ 64 ’0110’ 80 ’0111’ 96 ’1000’ 112 ’1001’ 128 ’1010’ 160 ’1011’ 192 ’ ...
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... DRA register is used to attenuate the level of audio output at the Right Channel using the but- terfly shown in Fig. 11. When the register is set to STA015-STA015B-STA015T 255 (0xFF), the achieved. A decimal unit correspond to an attenuation step of 1 dB. DLA Output Left Channel X + ...
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... STA015-STA015B-STA015T DRB Address: 0x49 (73) Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB DRB7 DRB6 DRB5 DRB4 DRB register is used to re-direct the Right Chan- nel on the Left mix both the Channels. ...
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... PF15 PF14 PF13 PF12 PF11 PF10 PF9 The registers are considered logically concate- nated and contain the fractional values for the PLL, for 44.1KHz reference frequency. (see also PLLFRAC_L and PLLFRAC_H regis- ters) ADPCM_SAMPLE_FREQ Address: 0x53 (83) Type: R/W STA015-STA015B-STA015T Software Reset: 0x00 Hardware Reset: 0x00 MSB ...
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... STA015-STA015B-STA015T The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCM_DIV = (O_FAC/64 bit mode ...
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... Interface format. After hw and sw reset the value is set to 0 corre- 2 sponding format. SCL (fig.14): used to select the Transmitter Serial Clock polarity. If set to ’1’ the data are sent on the STA015-STA015B-STA015T LSB SCL PREC (1) PREC (1) PCM order the LS bit is transmitted First ...
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... STA015-STA015B-STA015T PCMCROSS Address: 0x56 (86) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB The default configuration for this register is ’0x00’. MFSDF (X) Address: 0x61 (97) Type: R/W Software Reset: 0x07 Hardware Reset: 0x07 ...
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... AB5 AB4 AB3 AB2 AVERAGE_BITRATE is a read-only register and it contains the average bitrate of the incoming bit- stream. The value is rounded with an accuracy of 1 Kbit/sec. SOFTVERSION Address: 0x71 (113) Type: RO STA015-STA015B-STA015T MSB LSB SV7 SV6 SV5 b1 b0 After the STA015 boot, this register contains the ...
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... STA015-STA015B-STA015T BASS_FREQUENCY_LOW Address: 0x79 (121) Software Reset: 0x00 Hardware Reset: 0x00 MSB BF7 BF6 BF5 BF4 BF3 BF2 BASS_FREQUENCY_HIGH Address: 0x7A (122) Software Reset: 0x00 Hardware Reset: 0x00 MSB BF15 BF14 BF13 BF12 BF11 BF10 BF9 ...
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... STA015-STA015B-STA015T This register is used to select the enhancement or attenuation STA015 has to perform on Bass Frequency range at the digital signal. A decrement (increment decimal unit corre- sponds to a step of attenuation (enhancement) of 1.5dB. LSB The allowed Attenuation/Enhan cement range [-18dB, +18dB] ...
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... STA015-STA015B-STA015T TONE_ATTEN Address: 0x7D (125) Type: RW Software Reset: 0x00 Hardware Reset: 0x00 MSB TA7 TA6 TA5 TA4 TA3 TA2 In the digital output audio, the full signal is achieved with attenuation. For this rea- MSB ...
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... Ancillary Data Available The ISR is used by the microcontroller to under- stand when a new ancillary data block is avail- able. ADPCM_CONFIG Address: 0xB8 (184) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 STA015-STA015B-STA015T MSB This register controls ADPCM engine and how data must be compressed ...
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... STA015-STA015B-STA015T GPSO_CONF Address: 0xBA (186) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB GSP: GPSO Sclk polarity Using this bit the GPSO_SCLK polarity can be controlled. Clearing GSP bit data on GPSO_DATA line will be provided on the rising edge of GPSO_SCLK (sampling on falling edge) ...
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... Using this register the ADPCM interrupt capability can be properly configured. INTL0 - Interrupt Length INTL6 The interrupt length can be programmed, using this bits, from 128 system clock cycles STA015-STA015B-STA015T GPIO_CONF Address: 0xBF (191) Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 LSB MSB ...
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... STA015-STA015B-STA015T The STA015 contains 56 consecutive 8-bit regis- ters corresponding to the maximum number of ancillary data that may be contained in MPEG frame. The ANCCOUNT_L and ANCOUNT_H registers contain the number of ancillary data bits available within the current MPEG frame. To perform ancillary data reading a status regis- ...
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... OCLK) b) OCLK in input. OCLK (INPUT) SDO SCKT LRCLK Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns STA015-STA015B-STA015T t sdo t sckt t lrclk D98AU969 Pad-timing versus load Load (pF 100 Cload_XXX is the load the XXX output ...
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... STA015-STA015B-STA015T 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0 BIT_EN SCKR IGNORED SDI 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1 BIT_EN SCKR IGNORED SDI tsdi_setup_min= 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT This is an asynchronous input used in ”broadcast’ mode. ...
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... PLL FRAC_H, PLL FRAC_L } set { MFS DF_441, MFSDF } set PLL CTRL set SCLK_POL set DATA_REQ_ENABLE set REQ_POL set RUN STA015-STA015B-STA015T t reset_low_min PCM OUTPUT INTERFACE THE OVERALL CONFIGURATION SETTING STEPS ARE INCLUDED IN THE STA015 CONFIGURATION FILE AND CAN BE DOWNLOADED PLL IN ONE STEP. CONFIGURATION ...
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... STA015-STA015B-STA015T Table 5: PLL Configuration Sequence For 10MHz Input Clock 256 Oversapling Clock REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL Table 6: PLL Configuration Sequence For 10MHz Input Clock 384 Oversapling Rathio REGISTER NAME ADDRESS ...
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... Oversapling Rathio REGISTER NAME ADDRESS 6 reserved 11 reserved 97 MFSDF (x) 80 MFSDF-441 101 PLLFRAC-H 82 PLLFRAC-441-H 100 PLLFRAC-L 81 PLLFRAC-441-L 5 PLLCTRL STA015-STA015B-STA015T Table 11: PLL Configuration Sequence For 14.7456MHz Input Clock 384 Oversapling Rathio REGISTER VALUE ADDRESS 11 6 reserved 3 11 reserved 6 97 MFSDF ( MFSDF-441 3 101 ...
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... STA015-STA015B-STA015T 5.6. STA015 CONFIGURATION FILE FORMAT The STA015 Configuration File is an ASCII format. An example of the file format is the following 128 15 ............ sequence of rows and each one can be interpreted The first part of the row is the I C address (register) and the second one is the I To download the STA015 configuration file into the device, a sequence of write operation to STA015 I interface must be performed ...
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... DIM. MIN. TYP. MAX. MIN. TYP. A 2.65 a1 0.1 0.3 0.004 b 0.35 0.49 0.014 b1 0.23 0.32 0.009 C 0.5 0.020 c1 45 (typ.) D 17.7 18.1 0.697 E 10 10.65 0.394 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 L 0.4 1.27 0.016 S 8 (max.) STA015-STA015B-STA015T OUTLINE AND MECHANICAL DATA MAX. 0.104 0.012 0.019 0.013 0.713 0.419 0.299 0.050 SO28 41/44 ...
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... STA015-STA015B-STA015T mm DIM. MIN. TYP. MAX. MIN. A 1.60 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 B 0.30 0.37 0.45 0.012 C 0.09 0.20 0.004 D 12.00 D1 10.00 D3 8.00 e 0.80 E 12.00 E1 10.00 E3 8.00 L 0.45 0.60 0.75 0.018 L1 1.00 K (min.), 3.5 (typ.), 7 (max 42/44 inch OUTLINE AND TYP. MAX. MECHANICAL DATA 0.063 0.006 0.055 0.057 0.014 0.018 0.008 0.472 0.394 0.315 0.031 ...
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... D1 5.600 0.220 e 0.800 0.031 E 8.000 0.315 E1 5.600 0.220 f 1.200 0.047 BALL 1 IDENTIFICATION (64 PLACES) e STA015-STA015B-STA015T OUTLINE AND MECHANICAL DATA MAX. 0.067 0.018 Body 1.7mm LFBGA64 0. LFBGA64M D E 43/44 ...
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... STA015-STA015B-STA015T Information furnished is believed to be accurate and reliable. However, STMicroelectroni cs assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...