A6850 ALTERA [Altera Corporation], A6850 Datasheet - Page 10

• Manufacturer Part Number: A6850
• Description: Asynchronous Communications Interface Adapter
• Manufacturer: ALTERA [Altera Corporation]

a6850 Asynchronous Communications Interface Adapter Data Sheet
Figure 3. Read & Write Cycle Waveforms
90
The X indicates “don’t care.”
Control signal setup
rnw
do
cs
rs
di
e
X
X
X
Undefined
Receiver Operation
Receiver operation includes the following functions:
Start Bit Detection
The a6850 begins receiving data when a start bit is detected. A start bit is
a logic low over the rxdata input, and is sampled on each rising edge of
the rxclk signal. Once the a6850 detects a logic low, it begins counting
the logic low samples according to the specified divide-by mode (i.e., -1,
-16, or -64).
For example, after detecting a logic low in divide-by-1 mode, the a6850
assumes the next rising edge is data. After detecting a logic low in divide-
by-16 mode, however, the a6850 counts 8 clock edges and samples again.
The data must still be a logic low. At this point, the a6850 assumes the
data and clock are synchronized, and samples data every 16 clock edges
thereafter. Divide-by-64 mode is similar to divide-by-16, with the logic
low sampled at the first rising edge and the 32nd rising edge of rxclk.
Data is then sampled every 64 rising edges.
Start bit detection
Data bit sampling
Parity & stop bit detection
Error detection
Receive data register transfer
Read
Valid
110
Valid
Control signal setup
X
X
X
X
Undefined
Valid
110
Write
Altera Corporation
Valid
Data input setup
X
X
X
X