E-L8150 STMICROELECTRONICS [STMicroelectronics], E-L8150 Datasheet
E-L8150
Related parts for E-L8150
E-L8150 Summary of contents
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... Torque optimizer terminal controlled by analog voltage input ■ V regulator output terminalExternal HVIC bootstrap capacitor pre-charge function Order codes Part number E-L8150 E-L8150TR March 2006 ■ External HVIC bootstrap capacitor refresh function during 120 degree drive (rectangular drive). ■ This means both upper and lower chopping and low side current recirculation for rectangular drive ...
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... Pins description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 Operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 Electrical characteristcs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 Drive stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.3 I 4.4 Hall Sensor Input Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 Protection Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.6 PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.7 System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.8 External HVIC Bootstrap Capacitor Initialization . . . . . . . . . . . . . . . . . . . 14 4.9 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.10 Others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Operating description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 Free-Run (FS) and Reset (SD) functions . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 Smooth Drive and Control logic description ...
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... L8150 8 Input Output Pins Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Contents 3/37 ...
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... Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Operating condition Table 4. Supply Voltage Terminal VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 5. Regulator Output Terminal Vreg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 6. Driver Output Terminal UH,VH,WH,UL,VL, Table 7. Dead Time Select Terminal Table 8. Hall Sensor Input Terminal HUP,HUN,HVP,HVN,HWP,HWN . . . . . . . . . . . . . . . . . . . . . . . 9 Table 9. Torque Optimizer Input Terminal T. Table 10. Over Current Sense Input Terminal Table 11 ...
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... Pins: INTout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 28. Pins: OSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 29. Pins: FG, DM, FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 30. ESD clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 31. Recirculation diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 32. Pins Figure 33. Pins: HWN, HWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 34. Pins: HUN, HUVP, HVN, HVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Figure 35. Pins: UH, UL, VH, VL, WH Figure 36. SO-28 Mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 List of figures 5/37 ...
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... Block diagram & pins description 1 Block diagram & pins description 1.1 Block diagram Figure 1. Block diagram 1.2 Pins description Figure 2. Pins connection (top view) 6/ GND VCC VREG INTOUT INTINN INTINP SDT 8 21 FAULT HUP 9 20 ...
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... GND Function External sense resistance pin W bridge high-side MOS output command W bridge low-side MOS output command V bridge high-side MOS output command V bridge low-side MOS output command U bridge high-side MOS output command U bridge low-side MOS output command Dead time selection input pin ...
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... Electrical specifications 2.1 Absolute maximum ratings Table 2. Absolute maximum ratings No. Item 1 VCC supply voltage 2 FG terminal voltage 3 FAULT terminal voltage 4 DM terminal voltage 5 FG, FAULT, DM currents 6 RF voltage 7 Other pin voltage 8 Inject current Operating ambient 9 temp. 10 Junction temp. 11 Storage temp. 12 Latch up tolerance ...
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... Hall Sensor Input Terminal HUP,HUN,HVP,HVN,HWP,HWN No. Item 1 input bias current common mode input 2 range 3 input voltage range 4 hall input sensitivity 5 hysteresis width 6 hysteresis L -> hysteresis H -> L =15V unless otherwise specified REG Symbol Terminal I VCC CC1-1 Terminal Min Typ VREG 4.7 5.0 VREG 40 VREG 5 VREG 0 ...
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... Table 14. OSC Terminal OSC No. Item Symbol Terminal 1 Current setting V osc 2 PWM frequency F pwm Table 15. OP Amp Input Output Terminal INTin+, INTin-, INTout (note 3, note 4) No. Item 1 H level output voltage 2 L level output voltage 3 input bias current 4 offset 10/37 Symbol Terminal Min T ...
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... If 20mA is a problem for design because of power dissipation etc., it can be reduced to something like 5mA 2 one input is set at 2.5V by means of a resistor divider. The other input moves from 0V to Vreg. The Hall comparator must operate correctly for all its input range. 3 Opamp need to be designed to meet with Kval control by VSP. ...
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... Electrical characteristcs Figure 3. Kval control by VSP Figure 4. External circuit for Vsp control 12/37 INT amp network (suggested) 90.9K Vsp 53.6K 46.4K 22.1K Vreg 31.6K L8150 Vo ...
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... There are 2 types of application, Hall device and Hall IC Hall Device application: differential inputs with some bias Hall IC application: one input is fixed around VREG/2 by resistor divider between VREG and GND the other input comes from Hall IC whose span is between 0 and 5V. General description 13/37 ...
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... External HVIC Bootstrap Capacitor Initialization Lower arm ALL ON (3 outputs for low side are High, 3 outputs for High side are GND) when VSP becoming ON (free run release), (while this initialization should not be done when VSP becoming OFF) initializing time is 0.333 - 0.5 msec. ...
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... L8150 A maximum current of 5mA can be injected into OV protection terminal in case VCC = OFF and VDC = ON without damaging the device. Moreover the output does not cause malfunctioning (all power Transistors are OFF). A maximum current of 5mA can be injected into TO terminal from external circuit during VCC OFF without damaging the device ...
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... The second one (SD) switches from High to Low, thus enabling normal device operation. When SD is High it acts as a reset signal for the whole logic block and as a stand-by signal for the system oscillator and the speed amplifier High is generated by a low voltage condition on VREG ...
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... The value (expressed in electrical degrees, hereafter referred to as degrees) can be chosen applying an analog voltage to TO pin, that will be internally converted using a 4-bit A/D. The phase shift range is from 2 degrees with a 2.5-degrees step reference the correspondence between phase shift values and analog voltages is reported in (Figure 6) in case of forward rotation (CW) ...
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... The 4-bit A/D has an internal hysteresis so that "Analog high thresholds" are the A/D thresholds applying a rising edge on TO pin, the "Analog low thresholds" are the A/D thresholds applying a falling edge on TO pin. The applied phase shift "moves" the voltage profile with respect to the Hall effect sensor in the direction indicated by the arrows in the picture. 18/37 Analog low threshold [V] < ...
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... Smooth Drive Pattern (Reverse) In case sinusoidal mode cannot be applied, a rectangular pattern will be applied, that is driving one phase fixed to GND, one phase in tri-state while the other is switching from low to high with a duty cycle depending on the ADC conversion , max. duty cycle about 95%, according to the following diagram: Figure 9 ...
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... The motor is rotating and its frequency is bigger than the one used to switch between rectangular and sinusoidal driving pattern In case 1) even if the detected rotation direction is different from the desired direction, the current limiter control method is to force two phases to GND and one phase is left in high impedance state. In case 2) the possible situations can be the following: ...
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... HallW) and generates a set of three internal signals used inside the digital part of the circuit (PosFil). Figure 11. Filtering circuit From input comparator In order to simplify the explanation of the filtering circuit a signal Pos will be defined that can assume 7 different values according to the following table: Table 22. 7 different values of the signal Pos HallU ...
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... PosFil The filter working principle is explained in the previous diagram component of the filter circuit is a 12-bit counter that is reset (to the value 0) whenever the PosFil signal is equal to the Pos one. When the two signals are different (meaning that a transition is happening), the counter will start counting as long as one of the following conditions will occur: ● ...
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... This signal is amplified by an inverting amplifier which takes as reference a voltage derived from VREG through a voltage divider. The amplifier output is the input signal of an 8-bit ADC which generates the digital word KVAL, used to determine the duty cycle value according to the following Speed control: Intout 0-0 ...
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... Tel N.B. TelMAX is equal to TMAX used in the previous sections of this document. After this saturation time the logic has decided precharge function, and for a period of time given by the following equation all the output logic signals UL,VL,WL become high while the signals UH, VH, WH are low. ...
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... The next filtering time used for the Hall commutation is a fraction of the elapsed time between the first two Hall effect commutations, according to the previous T This filtering time is used until the first rising edge on signal HallU is detected and a zero- crossing signal is generated. After that the filtering time used is a fraction of the elapsed time between the last two detected zero-crossing signals, in other words between the second Hall effect commutation and the rising edge on signal HallU ...
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... This situation is similar to the one described before, except DM behaviour. Let's suppose the FS signal high, which means all phases in high impedance state. Even if the signal FS is high, the logic is able to detect if the motor is rotating in the desired direction or not. So when the signal coming from the FS comparator has a falling edge, by default a zero- crossing signal is generated and the DM signal is already low, indicating that the detected direction is not equal to desired direction ...
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... Let's consider a startup sequence forced by FS-Comparator, supposing the motor rotating slowly. When the signal coming from the FS comparator has a falling edge, the logic waits for a Hall effect commutation for a period of time equal to TelMAX/ Hall effect commutation happens during this time, the behaviour is the one described in the previous section, when a startup sequence with motor stopped is described ...
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... When the SD signal has a falling edge (corresponding to a VREG signal that's crossing the lower voltage protection), the logic can produce a ZC signal, depending on FS signal behaviour induced by Vsp voltage value. In any case, even signal is produced, if the motor is stopped and no Hall effect commutation is detected, the counter reaches its saturation time TelMAX/6 and the system evolves like in the situation described in previous startup sequence with motor stopped ...
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... Since the signal SD is high and considering that this is the reset signal for the whole logic part, the system is not able to detect if the motor is rotating in the desired direction or not and by default the DM signal will be high ...
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... HALL BUS FILTER TIME PHASES When the SD signal has a falling edge the logic waits for an Hall effect commutation. If the motor is rotating too quickly the next Hall effect commutation occurs before the filtering time has elapsed. This means that a new Hall filter count is performed and no Hall effect codification is ...
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... L8150 7 Application example Figure 22. Basic motor control circuit Application example 31/37 ...
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... Application example Figure 23. 3 phases motor control circuit 32/37 L8150 ...
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... L8150 8 Input Output Pins Interface In the following the simplified schematics of all the device pins. Figure 24. Pins: TSD, OV, SDT, INTinN, INTinP Figure 25. Pins: TO VREG TSD,OV,SDT, INTinN,INTinP Figure 26. Pins: RF VREG RF Figure 28. Pins: OSC VREG D01IN1271 TO D01IN1267 Figure 27. Pins: INTout D01IN1269 Figure 29. Pins: FG, DM, FAULT ...
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... Figure 34. Pins: HUN, HUVP, HVN, HVP VREG HUN,HUP HVN,HVP D01IN1277 34/37 Figure 31. Recirculation diode VCC ESD CLAMP GND Figure 33. Pins: HWN, HWP HWN,HWP D01IN1275 Figure 35. Pins: UH, UL, VH, VL, WH Test Mode DEVICE D01IN1274 VREG D01IN1276 VREG ON DURING POWER UP D01IN1278 L8150 VREG GND UH,UL ...
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... In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK trademark. ...
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... Revision history 10 Revision history Table 23. Document revision history Date 20-Mar-2006 36/37 Revision 1 Initial release. L8150 Changes ...
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