ADT7473_11 ONSEMI [ON Semiconductor], ADT7473_11 Datasheet - Page 12

• Manufacturer Part Number: ADT7473_11
• Description: dbCOOL Remote Thermal Monitor and Fan Control
• Manufacturer: ONSEMI [ON Semiconductor]

Read Operations
read protocols.
Receive Byte
register. The register address must have been previously set
up. In this operation, the master device receives a single byte
from a slave device, as follows:
is used to read a single byte of data from a register whose
address has previously been set by a send byte or write byte
operation. This operation is illustrated in Figure 22.
Alert Response Address
devices that allows an interrupting device to identify itself
to the host when multiple devices exist on the same bus.
output or an SMBALERT. One or more outputs can be
connected to a common SMBALERT line connected to the
master. If a device’s SMBALERT line goes low, the
following events occur:
•
•
•
•
alert response address, the master must read the status
registers, and the SMBALERT is cleared only if the error
condition is gone.
The ADT7473/ADT7473−1 uses the following SMBus
This operation is useful when repeatedly reading a single
In the ADT7473/ADT7473−1, the receive byte protocol
Alert response address (ARA) is a feature of SMBus
The SMBALERT output can be used as either an interrupt
Once the ADT7473/ADT7473−1 has responded to the
SMBALERT is pulled low.
The master initiates a read operation and sends the alert
response address (ARA = 0001 100). This is a general
call address that must not be used as a specific device
address.
The device whose SMBALERT output is low responds
to the alert response address, and the master reads its
device address. The address of the device is now known
and can be interrogated in the usual way.
If more than one device’s SMBALERT output is low,
the one with the lowest device address has priority in
accordance with normal SMBus arbitration.
1. The master device asserts a start condition on
2. The master sends the 7−bit slave address followed
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NO ACK on SDA.
6. The master asserts a stop condition on SDA, and
Figure 22. Single−Byte Read from a Register
SDA.
by the read bit (high).
the transaction ends.
S
1
ADDRESS
SLAVE
2
R
A
3
DATA
4
5 6
A P
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12
SMBus Timeout
feature. If there is no SMBus activity for 35 ms, the
ADT7473/ADT7473−1 assumes the bus is locked and
releases the bus. This prevents the device from locking or
holding the SMBus expecting data. Some SMBus
controllers cannot work with the SMBus timeout feature, so
it can be disabled.
Configuration Register 1 (0x40)
Bit 6, TODIS = 0; SMBus timeout enabled (default)
Bit 6, TODIS = 1; SMBus timeout disabled
Voltage Measurement Input
measurement channel and can also measure its own supply
voltage, VCC. Pin 14 can measure VCCP. The VCC supply
voltage measurement is carried out through the VCC pin
(Pin 3). The VCCP input can be used to monitor a chipset
supply voltage in computer systems.
Analog−to−Digital Converter
successive approximation, analog−to−digital converter.
(ADC) This has a resolution of 10 bits. The basic input range
is 0 V to 2.25 V, but the input has built−in attenuators to allow
measurement of V
allow for the tolerance of the supply voltage, the ADC
produces an output of 3/4 full scale (768 decimal or 300
hexadecimal) for the nominal input voltage and thus has
adequate headroom to deal with overvoltages.
Input Circuitry
in Figure 23. The input circuit consists of an input protection
diode, an attenuator, plus a capacitor to form a first order
low−pass filter that provides the input immunity to high
frequency noise.
Voltage Measurement Registers
Register 0x21, V
Register 0x22, V
V
and low limit register. Exceeding the programmed high or
low limit causes the appropriate status bit to be set.
Exceeding either limit can also generate SMBALERT
interrupts.
Register 0x46, V
Register 0x47, V
CCP
The ADT7473/ADT7473−1 includes an SMBus timeout
The ADT7473/ADT7473−1 has one external voltage
All analog inputs are multiplexed into the on−chip,
The internal structure for the V
Associated with the V
Limit Registers
Figure 23. Structure of Analog Inputs
V
CCP
CCP
CC
CCP
CCP
CCP
Reading = 0x00 default
Reading = 0x00 default
Low Limit = 0x00 default
High Limit = 0xFF default
17.5kΩ
without any external components. To
CCP
52.5kΩ
measurement channel is a high
CCP
analog input is shown
35pF