Z53C80SCSI ZILOG [Zilog, Inc.], Z53C80SCSI Datasheet - Page 8

• Manufacturer Part Number: Z53C80SCSI
• Description: SMALL COMPUTER SYSTEM INTERFACE (SCSI)
• Manufacturer: ZILOG [Zilog, Inc.]

Z
FUNCTIONAL DESCRIPTION (Continued)
Input Data Register. Address 6 (Read Only). The input
Data Register (Figure 7) is a read-only register that is used
to read latched data from the SCSI Bus. Data is latched
either during a DMA Target receive operation when /ACK
goes active or during a DMA Initiator receive when /REQ
goes active. The DMA Mode bit (Mode Register bit 1) must
be set before data can be latched in the Input Data
Register. This register is read under DMA control using
/RD and /DACK. Parity is optionally checked when the
Input Data Register is loaded.
Initiator Command Register. Address 1 (Read/Write).
The Initiator Command Register (Figures 8 and 9) are read
and write registers which assert certain SCSI Bus signals,
monitors those signals, and monitors the progress of bus
arbitration. Many of these bits are significant only when
being used as an Initiator; however, most can be used
during Target role operation.
8
Address: 6
ILOG
D7 D6 D5 D4 D3 D2 D1 D0
Figure 7. Input Data Register
(Read Only)
/DB0
/DB1
/DB2
/DB3
/DB4
/DB5
/DB6
/DB7
Address: 1
Address: 1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 8. Initiator Command Register
Figure 9. Initiator Command Register
(Read Only)
(Write Only)
(Register Read)
(Register Write)
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
Lost Arbitration
Arbitration in Progress
Assert /RST
Assert Data Bus
Assert /ATN
Assert /SEL
Assert /BSY
Assert /ACK
"0"
Test Mode
Assert /RST
PS97SCC0200
Z53C80 SCSI