SAK-TC1197-256F180E INFINEON [Infineon Technologies AG], SAK-TC1197-256F180E Datasheet - Page 59

• Manufacturer Part Number: SAK-TC1197-256F180E
• Description: 32-Bit Single-Chip Microcontroller
• Manufacturer: INFINEON [Infineon Technologies AG]

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2.6.4
Three options exist for the communication channel between Tools (e.g. Debugger,
Calibration Tool) and TC1197:
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2.6.5
Some manufacturing tests can be invoked by the application (e.g. after power-on) if
needed:
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2.6.6
To efficiently locate and identify faults after integration of a TC1197 into a system special
functions are available:
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Data Sheet
Changing the configuration is triggered by a single SFR access to maintain
consistency.
Overlay configuration switch does not require the TriCore to be stopped or
suspended.
Invalidation of the Data Cache (maintaining write-back data) can be done
concurrently with the same SFR.
256 KB additional Overlay RAM on Emulation Device.
The 256 KB Trace memory of the Emulation Device can optionally be used for
Overlay also.
A dedicated trigger SFR with 32 independent status bits is provided to centrally post
requests from application code to the host computer.
The host is notified automatically when the trigger SFR is updated by the TriCore or
PCP. No polling via a system bus is required.
Two wire DAP (Device Access Port) protocol for long connections or noisy
environments.
Four (or five) wire JTAG (IEEE 1149.1) for standardized manufacturing tests.
CAN (plus software linked into the application code) for low bandwidth deeply
embedded purposes.
DAP and JTAG are clocked by the tool.
Bit clock up to 40 MHz for JTAG, up to 80 MHz for DAP.
Hot attach (i.e. physical disconnect/reconnect of the host connection without reset of
the TC1197) for all interfaces.
Infineon standard DAS (Device Access Server) implementation for seamless,
transparent tool access over any supported interface.
Lock mechanism to prevent unauthorized tool access to critical application code.
Hardware-accelerated checksum calculation (e.g. for Flash content).
RAM tests optimized for the implemented architecture.
Boundary Scan (IEEE 1149.1) via JTAG and DAP.
Self-Test Support
FAR Support
Tool Interfaces
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Introduction
V1.1, 2009-05
TC1197