HCPL-5760-100 HP [Agilent(Hewlett-Packard)], HCPL-5760-100 Datasheet - Page 7

• Manufacturer Part Number: HCPL-5760-100
• Description: AC/DC to Logic Interface Hermetically Sealed Optocouplers
• Manufacturer: HP [Agilent(Hewlett-Packard)]

Typical Characteristics
Notes:
1. Maximum operating frequency is
2. Measured at a point 1.6 mm below
3. Current into/out of any single lead.
4. Surge input current duration is 3 ms at
5. Derate linearly above 100°C free-air
6. The 1.8 kΩ load represents 1 TTL unit
Hysteresis
Input Clamp Voltage
Bridge Diode
Forward Voltage
Input-Output Resistance
Input-Output Capacitance
Input Capacitance
Output Rise Time
(10-90%)
Output Fall Time
(90-10%)
defined when output waveform (Pin 6)
attains only 90% of V
kΩ, C
wave input signal.
seating plane.
120 Hz pulse repetition rate. Transient
input current duration is 10 µs at
120 Hz pulse repetition rate. Note that
maximum input power, P
observed.
temperature at a rate of 4.26 mW/°C.
Maximum input power dissipation of
195 mW allows an input IC junction
temperature of 150°C at an ambient
temperature of T
typical thermal resistance from
junction to ambient of θ
The typical thermal resistance from
junction to case is equal to 170°C/W.
Excessive P
device degradation.
load of 1.6 mA and the 4.7 kΩ pull-up
resistor.
L
= 15 pF using a 5 V square
Parameter
IN
and T
A
= 125°C with a
J
CC
may result in
JA
with R
IN
i
= 235°C/W.
, must be
L
= 1.8
All typical values are at T
Symbol
V
V
V
V
R
C
I
C
HYS
D1,2
D3,4
t
t
HYS
ILC
I-O
I-O
IN
r
f
10. This is a momentary withstand test,
11. The t
12. The t
13. Common mode transient immunity in
7. Logic low output level at Pin 6 occurs
8. The ac voltage is instantaneous
9. Device considered a two terminal
under the conditions of V
well as the range of V
V
output level at Pin 6 occurs under the
conditions of V
range of V
decreased below V
voltage.
device: Pins 1, 2, 3, 4 connected
together, Pins 5, 6, 7 8 connected
together.
not an operating condition.
measured from the 2.5 V level of the
leading edge of a 5.0 V input pulse (1
µs rise time) to the 1.5 V level on the
leading edge of the output pulse (see
Figure 7).
measured from the 2.5 V level of the
trailing edge of a 5.0 V input pulse (1
µs fall time) to the 1.5 V level on the
trailing edge of the output pulse (see
Figure 7).
Logic High level is the maximum
tolerable dV
IN
has exceeded V
PHL
PLH
-0.76
Typ.
0.62
0.73
10
1.2
1.1
2.0
0.5
50
10
12
propagation delay is
propagation delay is
IN
CM/dt
< V
IN
Units
TH+
mA
pF
pF
µs
µs
≤ V
of the common mode
Ω
V
V
TH-
A
TH+
= 25°C, V
IN
TH-
.
once V
. Logic high
> V
IN
as well as the
I
V
V
I
I
V
f = 1 MHz, V
f = 1 MHz; V
Pins 2 & 3, Pins 1 & 4 Open
HYS
IN
IN
≥ V
TH
HYS
ILC
I-O
IN
= -10 mA
= 3 mA (see schematic)
– once
has
= 500 Vdc
= I
= V
TH+
= V
CC
TH+
Conditions
= 5 V, unless otherwise specified.
as
2
TH+
- V
- I
- V
3
TH-
; V
I-O
IN
7
14. In applications where dV
15. D
16. Standard parts receive 100% testing at
17. Parameters shall be tested as part of
TH-
= 0 V,
= 0 Vdc
3
voltage, V
will remain in a Logic High state (i.e.,
V
immunity in Logic Low level is the
maximum tolerable dV
common mode voltage, V
that the output will remain in a Logic
Low state (i.e., V
Figure 8.
exceed 50,000 V/µs (such as static
discharge), a series resistor, R
should be included to protect the
detector IC from destructively high
surge currents. The recommended
value for R
allowable drop in V
and V
240 Ω.
and D
25°C (Subgroups 1 and 9). SMD,
Class H and Class K parts receive
100% testing at 25, 125, and -55°C
(Subgroups 1 and 9, 2 and 10 ,3 and
11, respectively.)
device initial characterization and after
process changes. Parameters shall be
guaranteed to the limits specified for
all lots not specifically tested.
= GND;
O
1
> 2.0 V). Common mode transient
and D
CC
4
are zener diodes.
) with a minimum value of
CM
2
CC
are Schottky diodes; D
, to ensure that the output
is 240 Ω per volt of
O
< 0.8 V). See
CC
Fig.
1
7
7
CM/dt
(between Pin 8
CM/dt
CM
of the
, to ensure
Note
CC
may
9
,
3