HD6417641 RENESAS [Renesas Technology Corp], HD6417641 Datasheet - Page 793
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HD6417641
Manufacturer Part Number
HD6417641
Description
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417641.pdf
(1036 pages)
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Table 19.11 SCIF Interrupt Sources
Note:
19.6
Note the following when using the SCIF.
1. SCFTDR Writing and TDFE Flag
2. SCFRDR Reading and RDF Flag
Interrupt
Source
ERI
RXI
BRI
TXI
The TDFE flag in the serial status register (SCFSR) is set when the number of transmit data
bytes written in the transmit FIFO data register (SCFTDR) has fallen below the transmit
trigger number set by bits TTRG1 and TTRG0 in the FIFO control register (SCFCR). After
TDFE is set, transmit data up to the number of empty bytes in SCFTDR can be written,
allowing efficient continuous transmission.
However, if the number of data bytes written in SCFTDR is equal to or less than the transmit
trigger number, the TDFE flag will be set to 1 again after being read as 1 and cleared to 0.
TDFE clearing should therefore be carried out when SCFTDR contains more than the transmit
trigger number of transmit data bytes.
The number of transmit data bytes in SCFTDR can be found from the upper 8 bits of the FIFO
data count register (SCFDR).
The RDF flag in the serial status register (SCFSR) is set when the number of receive data bytes
in the receive FIFO data register (SCFRDR) has become equal to or greater than the receive
trigger number set by bits RTRG1 and RTRG0 in the FIFO control register (SCFCR). After
RDF is set, receive data equivalent to the trigger number can be read from SCFRDR, allowing
efficient continuous reception.
However, if the number of data bytes in SCFRDR is equal to or greater than the trigger
number, the RDF flag will be set to 1 again if it is cleared to 0. RDF should therefore be
cleared to 0 after being read as 1 after all the receive data has been read.
*
Usage Notes
RXI interrupt by DR is only possible in the asynchronous mode.
Description
Interrupt initiated by receive error (ER)
Interrupt initiated by receive data FIFO full (RDF) or
data ready (DR)*
Interrupt initiated by break (BRK) or overrun error
(ORER)
Interrupt initiated by transmit FIFO data empty
(TDFE)
Section 19 Serial Communication Interface with FIFO (SCIF)
Rev. 4.00 Sep. 14, 2005 Page 743 of 982
DMAC
Activation
Not possible
Possible
Not possible
Possible
Priority on
Reset Release
High
Low
REJ09B0023-0400
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