ADA4896-2ACP-EBZ AD [Analog Devices], ADA4896-2ACP-EBZ Datasheet - Page 21

• Manufacturer Part Number: ADA4896-2ACP-EBZ
• Description: 1 nV/?Hz, Low Power
• Manufacturer: AD [Analog Devices]

Data Sheet
LOW NOISE, GAIN SELECTABLE AMPLIFIER
A gain selectable amplifier makes processing a wide range of
input signals possible. A traditional gain selectable amplifier
uses switches in the feedback loops connecting to the inverting
input. The switch resistances degrade the noise performance of
the amplifier, as well as adding significant capacitance on the
inverting input node. The noise and capacitance issues can be
especially bothersome when working with low noise amplifiers.
Also, the switch resistances contribute to nonlinear gain error,
which is undesirable.
Figure 52 presents an innovative switching technique used in
the gain selectable amplifier such that the 1 nV/Hz noise per-
formance of the
gain error is much reduced. With this technique, the user can
also choose switches with minimal capacitance to optimize the
bandwidth of the circuit.
In the circuit shown in Figure 52, the switches are implemented
with the
S2A are on, or S1B and S2B are on. In this example, when the
S1A and S2A switches are on, the first stage amplifier gain is +4.
When the S1B and S2B switches are on, the first stage amplifier
gain is +2. The first set of switches of the
the output side of the feedback loop, and the second set of switches
is used to sample at a point (V1 or V2) where switch resistances
and nonlinear resistances do not matter. In this way, the gain
error can be reduced while preserving the noise performance
of the ADA4896-2.
Note that the input bias current of the output buffer can cause
problems with the impedance of the S2A and S2B sampling
switches. Both sampling switches are not only nonlinear with
voltage but with temperature as well. If this is an issue, place the
unused switch of the
output buffer to balance the bias currents (see Figure 52).
In addition, the bias current of the input amplifier causes
an offset at the output that varies based on the gain setting.
Because the input amplifier and the output buffer are mono-
lithic, the relative matching of their bias currents can be used
ADG633
Figure 52. Using the
ADA4896-2
and are configured such that either S1A and
ADG633
V
IN
75Ω
is preserved while the nonlinear
R
G1
(S3B) in the feedback path of the
ADA4896-2
2
3
ADA4896-2
ADG633
and the
–5V
+5V
8
4
ADG633
225Ω
75Ω
R
R
is placed on
F2
F1
1
V
01
D1
to Construct a Low Noise, Gain Selectable Amplifier to Drive a Low Resistive Load
S1B
S1A
Rev. | Page 21 of 28
V1
V2
B
ADG633
R
BALANCE
150Ω
to cancel out the varying offset. Placing a resistor equal to the
difference between R
in a more constant offset voltage.
The following derivation shows that sampling at V1 yields the
desired signal gain without gain error. R
resistance. V2 can be derived using the same method.
Substituting Equation 1 into Equation 2, the following
derivation is obtained.
Note that if V
error, the buffered output V
error. Figure 53 shows the normalized frequency response of
the circuit at V
S2B
S2A
V
V1
V1
–12
–15
–18
–21
–24
–27
–30
–3
–6
–9
01
D2
6
3
0
0.1
=
=
ADA4896-2/ADA4897-1/ADA4897-2
=
USING S3B IS OPTIONAL
V
V
R
V
V
6
5
S
IN
V
L
01
IN
= ±5V
= 1kΩ
ADA4896-2
IN
= 100mV p-p
01
×
×
S3B
02
×
Figure 53. Frequency Response of V
yields the desired signal gain without gain
⎛
⎜
⎜
⎝
⎛
⎜
⎜
⎝
.
–5V
+5V
8
4
1
⎛
⎜
⎜
⎝
R
1
+
F1
+
R
R
F2
R
1
+
F1
G1
D3
F1
R
and R
R
F1
+
G1
⎞
⎟
⎟
⎠
FREQUENCY (MHz)
R
7
V
R
ADG633
+
G1
02
+
02
G1
R
F1
R
will also be free from gain
S1
in series with Switch S2A results
S1
⎞
⎟
⎟
⎠
⎞
⎟
⎟
⎠
10
R
G = +4
L
S
denotes the switch
02
/V
100
IN
G = +2
500
(7)
(8)
(9)